AM79C978VCSLASHW datasheet(68/261 Pages) AMD

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Am79C978

which the SQE Test message is expected, the

Am79C978 controller will not respond to receive carrier

sense.

See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1):

“At the conclusion of the output function, the DTE

opens a time window during which it expects to see

the signal_quality_error signal asserted on the

Control In circuit. The time window begins when

the

CARRIER_STATUS

becomes

CARRIER_OFF. If execution of the output function

does not cause CARRIER_ON to occur, no SQE

test occurs in the DTE. The duration of the window

shall be at least 4.0

µs but no more than 8.0 µs.

During the time window the Carrier Sense Function

is inhibited.”

TheAm79C978 controller implements a carrier sense

“blinding” period of 4.0

µs length starting from the deas-

sertion of carrier sense after transmission. This effec-

tively means that when transmit two-part deferral is

enabled (DXMT2PD is cleared), the IFS1 time is from

4 ms to 6 ms after a transmission. However, since IPG

shrinkage below 4 ms will rarely be encountered on a

correctly configured network, and since the fragment

size will be larger than the 4 ms blinding window, the

IPG counter will be reset by a worst case IPG shrink-

age/fragment scenario and the Am79C978 controller

will defer its transmission. If carrier is detected within

the 4.0 to 6.0 ms IFS1 period, the Am79C978 controller

will not restart the “blinding” period, but only restart

IFS1.

Collision Handling

Collision detection is performed and reported to the

MAC engine via the COL input pin.

If a collision is detected before the complete preamble/

SFD sequence has been transmitted, the MAC engine

will complete the preamble/SFD before appending the

jam sequence. If a collision is detected after the pream-

ble/SFD has been completed, but prior to 512 bits

being transmitted, the MAC engine will abort the trans-

mission and append the jam sequence immediately.

The jam sequence is a 32-bit all zeros pattern.

The MAC engine will attempt to transmit a frame a total

of 16 times (initial attempt plus 15 retries) due to normal

collisions (those within the slot time). Detection of colli-

sion will cause the transmission to be rescheduled to a

time determined by the random backoff algorithm. If a

single retry was required, the 1 bit will be set in the

transmit frame status. If more than one retry was re-

quired, the MORE bit will be set. If all 16 attempts ex-

perienced collisions, the RTRY bit will be set (1 and

MORE will be clear), and the transmit message will be

flushed from the FIFO. If retries have been disabled by

setting the DRTY bit in CSR15, the MAC engine will

abandon transmission of the frame on detection of the

first collision. In this case, only the RTRY bit will be set,

and the transmit message will be flushed from the

FIFO.

If a collision is detected after 512 bit times have been

transmitted, the collision is termed a late collision. The

MAC engine will abort the transmission, append the

jam sequence, and set the LCOL bit. No retry attempt

will be scheduled on detection of a late collision, and

the transmit message will be flushed from the FIFO.

The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires

use of a “truncated binary exponential backoff” algo-

rithm, which provides a controlled pseudo random

mechanism to enforce the collision backoff interval,

before retransmission is attempted.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

“At the end of enforcing a collision (jamming), the

CSMA/CD sublayer delays before attempting to re-

transmit the frame. The delay is an integer multiple

of slot time. The number of slot times to delay be-

fore the nth retransmission attempt is chosen as a

uniformly distributed random integer r in the range:

≤ r < 2k Where k = Min (N,10).”

TheAm79C978 controller provides an alternative algo-

rithm, which suspends the counting of the slot time/IPG

during the time that receive carrier sense is detected.

This aids in networks where large numbers of nodes

are present, and numerous nodes can be in collision. It

effectively accelerates the increase in the backoff time

in busy networks and allows nodes not involved in the

collision to access the channel, while the colliding

nodes await a reduction in channel activity. Once chan-

nel activity is reduced, the nodes resolving the collision

time-out their slot time counters as normal.

This modified backoff algorithm is enabled when EMBA

(CSR3, bit 3) is set to 1.

Transmit Operation

The transmit operation and features of the Am79C978

controller are controlled by programmable options.

TheAm79C978 controller offers a large transmit FIFO

to provide frame buffering for increased system la-

tency, automatic retransmission with no FIFO reload,

and automatic transmit padding.

Transmit Function Programming

Automatic transmit features such as retry on collision,

FCS generation/transmission, and pad field insertion

can all be programmed to provide flexibility in the (re-)

transmission of messages.

Disable retry on collision (DRTY) is controlled by the

DRTY bit of the Mode register (CSR15) in the initializa-

tion block.

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