AM79C978VCSLASHW datasheet(91/261 Pages) AMD

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Am79C978

The PCI bus interface clock (CLK) is not required to be

running while the device is operating in Magic Packet

mode. Either of the INTA, the LED pins, or the PME sig-

nal may be used to indicate the receipt of a Magic

Packet frame when the CLK is stopped. If the system

wishes to stop the CLK, it will do so after enabling the

Magic Packet mode.

CAUTION: To prevent unwanted interrupts from other

active parts of the controller, care must be taken to

mask all likely interruptible events during Magic Packet

mode. An example would be the interrupts from the

Media Independent Interface, which could occur while

the device is in Magic Packet mode.

IEEE 1149.1 (1990) Test Access Port

Interface

An IEEE 1149.1-compatible boundary scan Test Ac-

cess Port is provided for board-level continuity test and

diagnostics. All digital input, output, and input/output

pins are tested. The following paragraphs summarize

the IEEE 1149.1-compatible test functions imple-

mented in the controller.

Boundary Scan Circuit

The boundary scan test circuit requires four pins (TCK,

TMS, TDI, and TDO), defined as the Test Access Port

(TAP). It includes a finite state machine (FSM), an in-

struction register, a data register array, and a power-on

reset circuit. Internal pull-up resistors are provided for

the TDI, TCK, and TMS pins.

TAP Finite State Machine

The TAP engine is a 16-state finite state machine

(FSM), driven by the Test Clock (TCK), and the Test

Mode Select (TMS) pins. An independent power-on

reset circuit is provided to ensure that the FSM is in the

TEST_LOGIC_RESET state at power-up. Therefore,

the TRST is not provided. The FSM is also reset when

TMS and TDI are high for five TCK periods.

Supported Instructions

In addition to the minimum IEEE 1149.1 requirements

(BYPASS, EXTEST, and SAMPLE instructions), three

additional instructions (IDCODE, TRIBYP, and SET-

BYP) are provided to further ease board-level testing.

All unused instruction codes are reserved. See Table

18 for a summary of supported instructions.

Instruction Register and Decoding Logic

After the TAP FSM is reset, the IDCODE instruction is

always invoked. The decoding logic gives signals to

control the data flow in the data registers according to

the current instruction.

Boundary Scan Register

Each Boundary Scan Register (BSR) cell has two

stages. A flip-flop and a latch are used for the Serial

Shift Stage and the Parallel Output Stage, respectively.

There are four possible operation modes in the BSR

cell shown in Table 19.

Other Data Registers

Other data registers are the following:

1. Bypass register (1 bit)

2. Device ID register (32 bits) (Table 20).

Note: The content of the Device ID register is the

same as the content of CSR88.

Table 18.

IEEE 1149.1 Supported Instruction

Summary

Instruction

Name

Instruction

Code

Description

Mode

Selected

Data

EXTEST

0000

External Test

Test

BSR

IDCODE

0001

ID Code

Inspection

Normal

ID REG

SAMPLE

0010

Sample

Boundary

Normal

BSR

TRIBYP

0011

Force Float

Normal

Bypass

SETBYP

0100

Control

Boundary to

I/0

Test

Bypass

BYPASS

1111

Bypass Scan

Normal

Bypass

Table 19.

BSR Mode Of Operation

Capture

Shift

Update

System Function

Table 20.

Device ID Register

Bits 31-28

Version

Bits 27-12

Part Number (0010 0110 0010 0110)

Bits 11-1

Manufacturer ID. The 11 bit manufacturer ID

cod for AMD is 00000000001 in accordance

with JEDEC publication 106-A.

Bit 0

Always a logic 1

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