ADE7758ARWRL datasheet(34/68 Pages) AD

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ADE7758

Rev. A | Page 34 of 68

The maximum output frequency (APCFNUM = 0x00 and

APCFDEN = 0x00) with full-scale ac signals on one phase is

approximately 16 kHz.

The ADE7758 incorporates two registers to set the frequency

of APCF (APCFNUM[11:0] and APCFDEN[11:0]). These are

unsigned 12-bit registers that can be used to adjust the frequency

of APCF by 1/212 to 1 with a step of 1/212. For example, if the

output frequency is 1.562 kHz, while the contents of CFDIV are

0 (0x000), then the output frequency can be set to 6.103 Hz by

writing 0xFF to the CFDEN register.

If 0 is written to any of the frequency division registers, the

divider would use 1 in the frequency division. In addition, the

ratio APCFNUM/ APCFDEN should be set not greater than

one to ensure proper operation. In other words, the APCF

output frequency cannot be higher than the frequency on the

DFC output.

The output frequency has a slight ripple at a frequency equal to

twice the line frequency. This is due to imperfect filtering of the

instantaneous power signal to generate the active power signal

(see the Active Power Calculation section). Equation 5 gives an

expression for the instantaneous power signal. This is filtered by

LPF2, which has a magnitude response given by Equation 11.

()

(11)

The active power signal (output of the LPF2) can be rewritten as

()

( t

IRMS

VRMS

IRMS

VRMS

cos

⎥

⎦

⎤

⎢

⎣

⎡

)

(12)

where f1 is the line frequency, for example, 60 Hz.

From Equation 12,

()

()t

IRMS

VRMS

IRMS

VRMS

cos

–

⎥

⎦

⎤

⎢

⎣

⎡

(13)

From Equation 13, it can be seen that there is a small ripple in

the energy calculation due to the sin(2ωt) component. Figure 69

shows this. The ripple gets larger with larger loads. Choosing a

lower output frequency for APCF during calibration by using a

large APCFDEN value and keeping APCFNUM relatively small

can significantly reduce the ripple. Also, averaging the output

frequency over a longer period of time achieves the same results.

–

E(t)

Vlt

× sin(4π× f

1× t)

π×f

1 +

2f1

Figure 69. Output Frequency Ripple

Line Cycle Active Energy Accumulation Mode

The ADE7758 is designed with a special energy accumulation

mode that simplifies the calibration process. By using the on-

chip zero-crossing detection, the ADE7758 updates the watt-hr

accumulation registers after an integer number of zero crossings

(Figure 70). The line active energy accumulation mode for watt-

hr accumulation is activated by setting the LWATT bit (Bit 0) of

the LCYCMODE register. The total energy over an integer

number of half-line cycles is written to the watt-hr accumulation

registers after the LINECYC number of zero crossings have

been detected. When using the line cycle accumulation mode,

the RSTREAD bit (Bit 6) of the LCYCMODE register should be

set to Logic 0.

ZXSEL0*

ZERO-CROSSING

DETECTION

(PHASE A)

ZXSEL1*

ZERO-CROSSING

DETECTION

(PHASE B)

ZXSEL2*

ZERO-CROSSING

DETECTION

(PHASE C)

*ZXSEL[0:2] ARE BITS 3 TO 5 IN THE LCYCMODE REGISTER

CALIBRATION

CONTROL

LINECYC[15:0]

WATTOS[11:0]

WG[11:0]

WDIV[7:0]

WATTHR[15:0]

ACCUMULATE ACTIVE POWER FOR

LINECYC NUMBER OF ZERO-CROSSINGS;

WATT-HR ACCUMULATION REGISTERS

ARE UPDATED ONCE EVERY LINECYC

NUMBER OF ZERO-CROSSINGS

ACTIVE POWER

Figure 70. ADE7758 Line Cycle Active Energy Accumulation Mode

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