ADE7758ARWRL datasheet(59/68 Pages) AD

59 / 68 page

ADE7758

Rev. A | Page 59 of 68

Address

[A6:A0]

Name

R/W1

Length

Default

Value

Description

0x0F

CVRMS

Phase C Voltage Channel RMS Register.

0x10

FREQ

Frequency of the Line Input Estimated by the Zero-Crossing Processing. It can

also display the period of the line input. Bit 7 of the LCYCMODE register

determines if the reading is frequency or period. Default is frequency. Data Bit 0

and Bit 1 of the MMODE register determine the voltage channel used for the

frequency or period calculation.

0x11

TEMP

Temperature Register. This register contains the result of the latest temperature

conversion. Please refer to the Temperature Measurement section for details on

how to interpret the content of this register.

0x12

WFORM

Waveform Register. This register contains the digitized waveform of one of the

six analog inputs or the digitized power waveform. The source is selected by

Data Bit 0 to Bit 4 in the WAVMODE register.

0x13

OPMODE

R/W

Operational Mode Register. This register defines the general configuration of the

ADE7758 (see Table 14).

0x14

MMODE

R/W

0xFC

Measurement Mode Register. This register defines the channel used for period

and peak detection measurements (see Table 15).

0x15

WAVMODE

R/W

Waveform Mode Register. This register defines the channel and sampling

frequency used in the waveform sampling mode (see Table 16).

0x16

COMPMODE

R/W

0x1C

This register configures the formula applied for the energy and line active energy

measurements (see Table 17).

0x17

LCYCMODE

R/W

0x78

This register configures the Line Cycle Accumulation Mode for WATT-HR, VAR-HR,

and VA-Hr (see Table 18).

0x18

MASK

R/W

The IRQ Mask Register. It determines if an interrupt event generates an active-

low output at the IRQ pin (see the ADE7758 Interrupts section).

0x19

STATUS

The IRQ Status Register. This register contains information regarding the source

of the ADE7758 interrupts (see the ADE7758 Interrupts section).

0x1A

RSTATUS

Same as the STATUS Register, except that its contents are reset to 0 (all flags

cleared) after a read operation.

0x1B

ZXTOUT

R/W

0xFFFF

Zero-Cross Timeout Register. If no zero crossing is detected within the time

period specified by this register, the interrupt request line (IRQ) goes active low

for the corresponding line voltage. The maximum timeout period is 2.3 seconds

(see the Zero-Crossing Detection section).

0x1C

LINECYC

R/W

0xFFFF

Line Cycle Register. The content of this register sets the number of half-line

cycles that the active, reactive, and apparent energies are accumulated for in the

line accumulation mode.

0x1D

SAGCYC

R/W

0xFF

SAG Line Cycle Register. This register specifies the number of consecutive half-

line cycles where voltage channel input may fall below a threshold level. This

threshold is specified by the SAGLVL register (see the Line Voltage SAG Detection

section).

0x1E

SAGLVL

R/W

SAG Voltage Level. This register specifies the detection threshold for the SAG

event. This register is common to all three phases’ line voltage SAG detections.

See the description of SAGCYC register for details.

0x1F

VPINTLVL

R/W

0xFF

Voltage Peak Level Interrupt Threshold Register. This register sets the level of the

voltage peak detection. Bit 5 to Bit 7 of the MMODE register determine which

phases are to be monitored. If the selected voltage phase exceeds this level, the

PKV flag in the IRQ status register is set.

0x20

IPINTLVL

R/W

0xFF

Current Peak Level Interrupt Threshold Register. This register sets the level of the

current peak detection. Bit 5 to Bit 7 of the MMODE register determine which

phases to are be monitored. If the selected current phase exceeds this level, the

PKI flag in the IRQ status register is set.

0x21

VPEAK

Voltage Peak Register. This register contains the value of the peak voltage

waveform that has occurred within a fixed number of half-line cycles. The

number of half-line cycles is set by the LINECYC register.

0x22

IPEAK

Current Peak Register. This register holds the value of the peak current waveform

that has occurred within a fixed number of half-line cycles. The number of half-

line cycles is set by the LINECYC register.

ADE7758ARWRL 数据表(PDF) 59 Page - Analog Devices

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