ADE7758ARWRL datasheet(57/68 Pages) AD

57 / 68 page

ADE7758

Rev. A | Page 57 of 68

ADE7758 SERIAL READ OPERATION

During a data read operation from the ADE7758, data is shifted

out at the DOUT logic output on the rising edge of SCLK. As

was the case with the data write operation, a data read must be

preceded with a write to the communications register.

With the ADE7758 in communications mode and CS logic low,

an 8-bit write to the communications register first takes place.

The MSB of this byte transfer must be a 0, indicating that the

next data transfer operation is a read. The seven LSBs of this

byte contain the address of the register that is to be read. The

ADE7758 starts shifting out of the register data on the next

rising edge of SCLK (see Figure 93). At this point, the DOUT

logic output switches from a high impedance state and starts

driving the data bus. All remaining bits of register data are

shifted out on subsequent SCLK rising edges. The serial

interface enters communications mode again as soon as the

read has been completed. The DOUT logic output enters a high

impedance state on the falling edge of the last SCLK pulse. The

read operation may be aborted by bringing the CS logic input

high before the data transfer is completed. The DOUT output

enters a high impedance state on the rising edge of CS.

When an ADE7758 register is addressed for a read operation,

the entire contents of that register are transferred to the serial

port. This allows the ADE7758 to modify its on-chip registers

without the risk of corrupting data during a multibyte transfer.

Note that when a read operation follows a write operation, the

read command (i.e., write to communications register) should

not happen for at least 1.1 µs after the end of the write operation.

If the read command is sent within 1.1 µs of the write operation,

the last byte of the write operation may be lost.

SCLK

t10

t13

DB0

DB7

DB0

DB7

DIN

DOUT

t11

t12

COMMAND BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

Figure 93. Serial Interface Read Timing Diagram

ADE7758ARWRL 数据表(PDF) 57 Page - Analog Devices

ADE7758ARWRL 数据表(HTML) 57 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载