ADE7758ARWRL datasheet(56/68 Pages) AD

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ADE7758

Rev. A | Page 56 of 68

The communications register is an 8-bit write-only register. The

MSB determines whether the next data transfer operation is a

read or a write. The seven LSBs contain the address of the register

to be accessed. See Table 12 for a more detailed description.

Figure 89 and Figure 90 show the data transfer sequences for a

read and write operation, respectively.

On completion of a data transfer (read or write), the ADE7758

once again enters into communications mode, i.e., the next

instruction followed must be a write to the communications

MULTIBYTE

COMMUNICATIONS REGISTER WRITE

DIN

SCLK

DOUT

READ DATA

ADDRESS

Figure 89. Reading Data from the ADE7758 via the Serial Interface

COMMUNICATIONS REGISTER WRITE

DIN

SCLK

ADDRESS

MULTIBYTE

READ DATA

Figure 90. Writing Data to the ADE7758 via the Serial Interface

A data transfer is completed when the LSB of the ADE7758

or from the ADE7758.

ADE7758 SERIAL WRITE OPERATION

The serial write sequence takes place as follows. With the

ADE7758 in communications mode and the CS input logic low,

a write to the communications register takes place first. The

MSB of this byte transfer must be set to 1, indicating that the

next data transfer operation is a write to the register. The seven

LSBs of this byte contain the address of the register to be written

to. The ADE7758 starts shifting in the register data on the next

falling edge of SCLK. All remaining bits of register data are

shifted in on the falling edge of the subsequent SCLK pulses

(see Figure 91).

As explained earlier, the data write is initiated by a write to the

communications register followed by the data. During a data

write operation to the ADE7758, data is transferred to all on-

chip registers one byte at a time. After a byte is transferred into

the serial port, there is a finite time duration before the content

in the serial port buffer is transferred to one of the ADE7758

on-chip registers. Although another byte transfer to the serial

port can start while the previous byte is being transferred to the

destination register, this second-byte transfer should not finish

until at least 900 ns after the end of the previous byte transfer.

This functionality is expressed in the timing specification t6 (see

Figure 91). If a write operation is aborted during a byte transfer

(CS brought high), then that byte is not written to the

destination register.

Destination registers may be up to 3 bytes wide (see the

Accessing the ADE7758 On-Chip Registers section). Therefore,

the first byte shifted into the serial port at DIN is transferred to

the most significant byte (MSB) of the destination register. If

the destination register is 12 bits wide, for example, a two-byte

data transfer must take place. The data is always assumed to be

right justified; therefore, in this case, the four MSBs of the first

byte would be ignored and the four LSBs of the first byte written

to the ADE7758 would be the four MSBs of the 12-bit word.

Figure 92 illustrates this example.

DIN

SCLK

COMMAND BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

1A6

DB7

DB0

DB7

DB0

Figure 91. Serial Interface Write Timing Diagram

SCLK

DIN

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

Figure 92. 12-Bit Serial Write Operation

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