ADE7758ARWRL datasheet(36/68 Pages) AD

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ADE7758

Rev. A | Page 36 of 68

to twice the line frequency. Because the ripple is sinusoidal

in nature, it is removed when the reactive power signal is

integrated over time to calculate the reactive energy.

The phase-shift filter has –90° phase shift when the integrator is

enabled and +90° phase shift when the integrator is disabled. In

addition, the filter has a nonunity magnitude response. Because

the phase-shift filter has a large attenuation at high frequency, the

reactive power is primarily for the calculation at line frequency.

The effect of harmonics is largely ignored in the reactive power

calculation. Note that because of the magnitude characteristic of

the phase shifting filter, the LSB weight of the reactive power

calculation is slightly different from that of the active power

calculation (see the Energy Registers Scaling section).

Reactive Power Gain Calibration

The average reactive power from the LPF output in each phase

can be scaled by ±50% by writing to the phase’s VAR gain

are twos complement, signed registers, and have a resolution of

0.024%/LSB. The function of the VAR gain registers is

expressed below.

Power

Reactive

Average

⎟

⎠

⎞

⎜

⎝

⎛ +

Gain

VAR

Output

LPF2

The output is scaled by –50% when the VAR gain registers

contents are set to 0x800 and the output is increased by +50%

by writing 0x7FF to the VAR gain register. This register can be

used to calibrate the reactive power (or energy) calculation in

the ADE7758 for each phase.

Reactive Power Offset Calibration

The ADE7758 incorporates a VAR offset register on each phase

(AVAROS, BVAROS, and CVAROS). These are signed twos

complement, 12-bit registers that are used to remove offsets in

the reactive power calculations. An offset may exist in the

power calculation due to crosstalk between channels on the

PCB or in the chip itself. The offset calibration allows the

contents of the reactive power register to be maintained at 0

when no reactive power is being consumed. The offset registers’

resolution is the same as the active power offset registers (see

the Apparent Power Offset Calibration section).

Sign of Reactive Power Calculation

Note that the average reactive power is a signed calculation. As

stated previously, the phase shift filter has –90° phase shift when

the integrator is enabled and +90° phase shift when the

integrator is disabled. Table 8 summarizes the relationship

between the phase difference between the voltage and the

current and the sign of the resulting VAR calculation.

The ADE7758 has a sign detection circuit for the reactive power

calculation. The REVPRP bit (Bit 18) in the interrupt status

phases changes. The phases monitored are selected by

TERMSEL bits in the COMPMODE register (see Table 17). If

the REVPRP bit is set in the mask register, the IRQ logic output

goes active low (see the ADE7758 Interrupts section). Note that

this bit is set whenever there is a sign change, i.e., the bit is set

for both a positive-to-negative change or a negative-to-positive

change of the sign bit.

Table 8. Sign of Reactive Power Calculation

Φ1

Integrator

Sign of Reactive Power

Between 0 to +90

Off

Positive

Between −90 to 0

Off

Negative

Between 0 to +90

Positive

Between −90 to 0

Negative

____________________________________________________

1 Φ is defined as the phase angle of the voltage signal minus the current

signal, i.e., Φ is positive if the load is inductive and negative if the load is

capacitive.

Reactive Energy Calculation

Reactive energy is defined as the integral of reactive power.

()dt

Energy

Reactive

∫

(19)

Similar to active power, the ADE7758 achieves the integration

of the reactive power signal by continuously accumulating the

reactive power signal in the internal 41-bit accumulation

registers. The VAR-hr registers (AVARHR, BVARHR, and

CVARHR) represent the upper 16 bits of these internal

registers. This discrete time accumulation or summation is

equivalent to integration in continuous time. Equation 20

expresses the relationship

()

⎭

⎬

⎫

⎩

⎨

⎧

∑

∫

∞

→

Lim

Energy

Reactive

(20)

where n is the discrete time sample number and T is the sample

period.

Figure 72 shows the signal path of the reactive energy accumula-

tion. The average reactive power signal is continuously added to

the internal reactive energy register. This addition is a signed

operation. Negative energy is subtracted from the reactive energy

the VAR divider register before they are added to the corre-

sponding VAR-hr accumulation registers. When the value in

the VARDIV[7:0] register is 0 or 1, the reactive power is

accumulated without any division. VARDIV is an 8-bit

unsigned register that is useful to lengthen the time it takes

before the VAR-hr accumulation registers overflow.

Similar to reactive power, the fastest integration time occurs

when the VAR gain registers are set to maximum full scale, i.e.,

0x7FF. The time it takes before overflow can be scaled by writing

to the VARDIV register and therefore it can be increased by a

maximum factor of 255.

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