ADE7758ARWRL datasheet(20/68 Pages) AD

20 / 68 page

ADE7758

Rev. A | Page 20 of 68

CURRENT CHANNEL ADC

Figure 41 shows the ADC and signal processing path for the

input IA of the current channels (same for IB and IC). In

waveform sampling mode, the ADC outputs are signed twos

complement 24-bit data-words at a maximum of 26.0 kSPS

(thousand samples per second). With the specified full-scale

analog input signal of ±0.5 V, the ADC produces its maximum

output code value (see Figure 41). This diagram shows a full-

scale voltage signal being applied to the differential inputs IAP

and IAN. The ADC output swings between 0xD7AE14

(−2,642,412) and 0x2851EC (+2,642,412).

Current Waveform Gain Registers

There is a multiplier in the signal path in the current channel

for each phase. The current waveform can be changed by ±50%

by writing a twos complement number to the 12-bit signed

current waveform gain registers (AIGAIN[11:0], BIGAIN[11:0],

and CIGAIN[11:0]). For example, if 0x7FF is written to those

registers, the ADC output is scaled up by +50%. On the other

hand, writing 0x800 scaled by the output –50%. The expression

below describes mathematically the function of the current

waveform gain registers.

⎟

⎠

⎞

⎜

⎝

⎛ +

Gain

Current

Content

Output

ADC

Waveform

Current

Changing the content of AIGAIN[11:0], BIGAIN[11:0], or

CIGAIN[11:0] affects all calculations based on its current, i.e., it

affects the phase’s active/reactive/apparent energy as well as its

current rms calculation. In addition, waveform samples are also

scaled accordingly.

Current Channel Sampling

The waveform samples of the current channel can be routed to

the WFORM register at fixed sampling rates by setting the

WAVSEL[2:0] bit in the WAVMODE register to 000 (binary).

The phase in which the samples are routed is set by setting the

PHSEL[1:0] bits in the WAVMODE register. Energy calculation

remains uninterrupted during waveform sampling.

When in waveform sample mode, one of four output sample

rates may be chosen by using Bit 5 and Bit 6 of the WAVMODE

13.0 kSPS, 6.5 kSPS, or 3.3 kSPS (see Table 16). By setting the

WSMP bit in the interrupt mask register to Logic 1, the interrupt

request output IRQ goes active low when a sample is available.

The timing is shown in Figure 40. The 24-bit waveform samples

are transferred from the ADE7758 one byte (8-bits) at a time,

with the most significant byte shifted out first.

READ FROM WAVEFORM

SGN

CURRENT CHANNEL DATA–24 BITS

12Hex

SCLK

DIN

DOUT

IRQ

Figure 40. Current Channel Waveform Sampling

The interrupt request output IRQ stays low until the interrupt

routine reads the reset status register (see ADE7758 Interrupts).

DIGITAL

INTEGRATOR*

GAIN[7]

ADC

REFERENCE

AIGAIN[11:0]

ACTIVE AND REACTIVE

POWER CALCULATION

WAVEFORM SAMPLE

CURRENT RMS (IRMS)

CALCULATION

IAP

IAN

PGA1

VIN

GAIN[4:3]

2.42V, 1.21V, 0.6V

GAIN[1:0]

×1, ×2, ×4

ANALOG

INPUT

RANGE

VIN

0.5V/GAIN

0.25V/GAIN

0.125V/GAIN

ADC OUTPUT

WORD RANGE

CHANNEL 1

(CURRENT WAVEFORM)

DATA RANGE

0xD7AE14

0x000000

0x2851EC

50Hz

CHANNEL 1 (CURRENT WAVEFORM)

DATA RANGE AFTER INTEGRATOR

(50Hz AND AIGAIN[11:0] = 0x000)

0xCB2E48

0x000000

0x34D1B8

60Hz

CHANNEL 1 (CURRENT WAVEFORM)

DATA RANGE AFTER INTEGRATOR

(60Hz AND AIGAIN[11:0] = 0x000)

0xD4176D

0x000000

0x2BE893

HPF

Figure 41. Current Channel Signal Path

ADE7758ARWRL 数据表(PDF) 20 Page - Analog Devices

ADE7758ARWRL 数据表(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载

链接网址

ADE7758ARWRL 数据表(PDF) 20 Page - Analog Devices

ADE7758ARWRL 数据表(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表 下载

链接网址

数据表下载