ADE7758ARWRL datasheet(62/68 Pages) AD

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ADE7758

Rev. A | Page 62 of 68

MEASUREMENT MODE REGISTER (0x14)

The configuration of the PERIOD and peak measurements made by the ADE7758 is defined by writing to the MMODE register.

Table 15 summarizes the functionality of each bit in the MMODE register.

Table 15. MMODE Register

Bit

Location

Bit

Mnemonic

Default

Value

Description

0 to 1

FREQSEL

These bits are used to select the source of the measurement of the voltage line frequency.

FREQSEL1

FREQSEL0

Source

Phase A

Phase B

Phase C

Reserved

2 to 4

PEAKSEL

These bits select the phases used for the voltage and current peak registers. Setting Bit 2 switches the

IPEAK and VPEAK registers to hold the absolute values of the largest current and voltage waveform

(over a fixed number of half-line cycles) from Phase A. The number of half-line cycles is determined by

the content of the LINECYC register. At the end of the LINECYC number of half-line cycles, the content

of the registers is replaced with the new peak values. Similarly, setting Bit 3 turns on the peak

detection for Phase B and Bit 4 is for Phase C. Note that if more than one bit is set, the VPEAK and

IPEAK registers can hold values from two different phases, i.e., the voltage and current peak are

independently processed (see the Peak Current Detection section).

5 to 7

PKIRQSEL

These bits select the phases used for the peak interrupt detection. Setting Bit 5 switches on the

monitoring of the absolute current and voltage waveform to Phase A. Similarly, setting Bit 6 turns on

the waveform detection for Phase B and Bit 7 is for Phase C. Note that more than one bit can be set for

detection on multiple phases. If the absolute values of the voltage or current waveform samples in

the selected phases exceeds the preset level specified in the PKVLVL or PKILVL registers, the

corresponding bit(s) in the STATUS registers are set (see the Peak Current Detection section).

WAVEFORM MODE REGISTER (0x15)

The waveform sampling mode of the ADE7758 is defined by writing to the WAVMODE register. Table 16 summarizes the functionality of

each bit in the WAVMODE register.

Table 16. WAVMODE Register

Bit

Location

Bit

Mnemonic

Default

Value

Description

0 to 1

PHSEL

These bits are used to select the phase of the waveform sample.

PHSEL[1:0]

Source

Phase A

Phase B

Phase C

Reserved

2 to 4

WAVSEL

These bits are used to select the type of waveform.

WAVSEL[2:0]

Source

Current

Voltage

Active Power Multiplier Output

Reactive Power Multiplier Output

VA Multiplier Output

-Others-

Reserved

5 to 6

DTRT

These bits are used to select the data rate.

DTRT[1:0]

Update Rate

26.0 kSPS (CLKIN/3/128)

13.0 kSPS (CLKIN/3/256)

6.5 kSPS (CLKIN/3/512)

3.3 kSPS (CLKIN/3/1024)

VACF

Setting this bit to Logic 1 switches the VARCF output pin to an output frequency that is

proportional to the total apparent power (VA). In the default state, Logic 0, the VARCF pin outputs

a frequency proportional to the total reactive power (VAR).

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