ST7MC1 datasheet(63/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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WINDOW WATCHDOG (Cont’d)

Figure 37. Window Watchdog Timing Diagram

10.1.6 Low Power Modes

10.1.7 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte,

the watchdog is always active and the WDGA bit in

the WDGCR is not used. Refer to the Option Byte

description.

10.1.8

Using

Halt

Mode

with

the

WDG

(WDGHALT option)

The following recommendation applies if Halt

mode is used when the watchdog is enabled.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG

reset immediately after waking up the microcon-

troller.

T6 bit

Reset

WDGWR

T[5:0] CNT downcounter

time

Refresh Window

Refresh not allowed

(step = 16384/fOSC2)

3Fh

Mode

Description

SLOW

No effect on Watchdog: The downcounter continues to decrement at normal speed.

WAIT

No effect on Watchdog: The downcounter continues to decrement.

HALT

OIE bit in

MCCSR

WDGHALT bit

in Option

Byte

No Watchdog reset is generated. The MCU enters Halt mode. The Watch-

dog counter is decremented once and then stops counting and is no longer

able to generate a watchdog reset until the MCU receives an external inter-

rupt or a reset.

If an interrupt is received (refer to interrupt table mapping to see interrupts

which can occur in halt mode), the Watchdog restarts counting after 256 or

4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset

state) unless Hardware Watchdog is selected by option byte. For applica-

tion recommendations see Section 10.1.8 below.

A reset is generated instead of entering halt mode.

ACTIVE

HALT

No reset is generated. The MCU enters Active Halt mode. The Watchdog

counter is not decremented. It stop counting. When the MCU receives an

oscillator interrupt or external interrupt, the Watchdog restarts counting im-

mediately. When the MCU receives a reset the Watchdog restarts counting

after 256 or 4096 CPU clocks.

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