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ST7MC1 数据表(PDF) 47 Page - STMicroelectronics |
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ST7MC1 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 308 page  ST7MC1/ST7MC2 47/308 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) (Cont’d) - ei0 (port D6..4) - ei0 (port D3..1) These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 0 = IPA Interrupt polarity for port D This bit is used to invert the sensitivity of the port D [6:4] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion IS31 IS30 External Interrupt Sensitivity IPA bit =0 IPA bit =1 00 Falling edge & low level Rising edge & high level 0 1 Rising edge only Falling edge only 1 0 Falling edge only Rising edge only 1 1 Rising and falling edge IS31 IS30 External Interrupt Sensitivity 0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge 1 |
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