ST7MC1 datasheet(100/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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SERIAL PERIPHERAL INTERFACE (cont’d)

10.4.5 Error Flags

10.4.5.1 Master Mode Fault (MODF)

Master mode fault occurs when the master de-

vice’s SS pin is pulled low.

When a Master mode fault occurs:

– The MODF bit is set and an SPI interrupt re-

quest is generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the device and disables the SPI periph-

eral.

– The MSTR bit is reset, thus forcing the device

into slave mode.

Clearing the MODF bit is done through a software

sequence:

1. A read access to the SPICSR register while the

MODF bit is set.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application

with multiple slaves, the SS pin must be pulled

high during the MODF bit clearing sequence. The

SPE and MSTR bits may be restored to their orig-

inal state during or after this clearing sequence.

Hardware does not allow the user to set the SPE

and MSTR bits while the MODF bit is set except in

the MODF bit clearing sequence.

In a slave device, the MODF bit can not be set, but

in a multimaster configuration the device can be in

slave mode with the MODF bit set.

The MODF bit indicates that there might have

been a multimaster conflict and allows software to

handle this using an interrupt routine and either

perform a reset or return to an application default

state.

10.4.5.2 Overrun Condition (OVR)

An overrun condition occurs when the master de-

vice has sent a data byte and the slave device has

not cleared the SPIF bit issued from the previously

transmitted byte.

When an Overrun occurs:

– The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

In this case, the receiver buffer contains the byte

sent after the SPIF bit was last cleared. A read to

the SPIDR register returns this byte. All other

bytes are lost.

The OVR bit is cleared by reading the SPICSR

10.4.5.3 Write Collision Error (WCOL)

A write collision occurs when the software tries to

write to the SPIDR register while a data transfer is

taking place with an external device. When this

happens, the transfer continues uninterrupted and

the software write will be unsuccessful.

Write collisions can occur both in master and slave

mode. See also Section 10.4.3.2 Slave Select

Management.

Note: A "read collision" will never occur since the

received data byte is placed in a buffer in which

access is always synchronous with the CPU oper-

ation.

The WCOL bit in the SPICSR register is set if a

write collision occurs.

No SPI interrupt is generated when the WCOL bit

is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software

sequence (see Figure 60).

Figure 60. Clearing the WCOL Bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

Read SPICSR

Read SPIDR

2nd Step

SPIF = 0

WCOL = 0

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

WCOL = 0

Read SPICSR

Read SPIDR

Note: Writing to the SPIDR register in-

stead of reading it does not reset the

WCOL bit.

RESULT

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