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ST7MC1 数据表(PDF) 38 Page - STMicroelectronics |
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ST7MC1 数据表(HTML) 38 Page - STMicroelectronics |
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38 / 308 page  ST7MC1/ST7MC2 38/308 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit. MCC BEEP CONTROL REGISTER (MCCBCR) Read/Write Reset Value: 0000 0000 (00h) Bit 7:4 = Reserved, must be kept cleared. Bit 3 = ADSTS A/D Converter Sample Time Stretch This bit is set and cleared by software to enable or disable the A/D Converter sample time stretch fea- ture. 0: AD sample time stretch disabled (for standard impedance analog inputs) 1 AD sample time stretch enabled (for high imped- ance analog inputs) Bit 2 = ADCIE A/D Converter Interrupt Enable This bit is set and cleared by software to enable or disable the A/D Converter interrupt. 0: AD Interrupt disabled 1 AD Interrupt enabled Bit 1:0 = BC[1:0] Beep control These 2 bits select the PF1 pin beep capability. The beep output signal is available in ACTIVE- HALT mode but has to be disabled to reduce the consumption. Table 5. Main Clock Controller Register Map and Reset Values 70 00 00 AD- STS ADC IE BC1 BC0 BC1 BC0 Beep mode with fOSC2=8MHz 00 Off 01 ~2-KHz Output Beep signal ~50% duty cycle 10 ~1-KHz 1 1 ~500-Hz Address (Hex.) Register Label 7 654 321 0 0040h SICSR, page0 Reset Value PAGE 0 VDIE 0 VDF 0 LVDRF x0 CFIE 0 CSSD 0 WDGRF x 0040h SICSR, page1 Reset Value PAGE 00 VCOEN 0 LOCK x PLLEN 00 CKSEL 00 002Ch MCCSR Reset Value MCO 0 CP1 0 CP0 0 SMS 0 TB1 0 TB0 0 OIE 0 OIF 0 002Dh MCCBCR Reset Value 0 000 ADSTS 0 ADCIE 0 BC1 0 BC0 0 1 |
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