ST7MC1 datasheet(34/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.3.5 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 0)

Read/Write

Reset Value: 000x 000x (00h)

Bit 7 = PAGE SICSR Register Page Selection

This bit selects the SICSR register page. It is set

and cleared by software

0: Access to SICSR register mapped in page 0.

1: Access to SICSR register mapped in page 1.

Bit 6 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables

an interrupt to be generated when the AVDF flag

changes (toggles). The pending interrupt informa-

tion is automatically cleared when software enters

the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware.

If the VDIE bit is set, an interrupt request is gener-

ated when the AVDF bit changes value.

0: VDD over VIT+ (AVD) threshold

1: VDD under VIT-(AVD) threshold

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware (LVD re-

set) and cleared by software (writing zero). See

WDGRF flag description for more details. When

the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

Bit 3 = Reserved, must be kept cleared.

Bit 2 = CSSIE Clock security syst

interrupt enable

This bit enables the interrupt when a disturbance

is detected by the Clock Security System (CSSD

bit set). It is set and cleared by software.

0: Clock security system interrupt disabled

1: Clock security system interrupt enabled

When the PLL is disabled (PLLEN=0), the CSSIE

bit has no effect.

Bit 1 = CSSD Clock security system detection

This bit indicates a disturbance on the main clock

signal (fOSC): the clock stops (at least for a few cy-

cles). It is set by hardware and cleared by reading

the SICSR register when the original oscillator re-

covers.

0: Safe oscillator is not active

1: Safe oscillator has been activated

When the PLL is disabled (PLLEN=0), the CSSD

bit value is forced to 0.

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hard-

ware (watchdog reset) and cleared by software

(writing zero) or an LVD Reset (to ensure a stable

cleared state of the WDGRF flag when CPU

starts).

Combined with the LVDRF flag information, the

flag description is given by the following table.

Application notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure.

In this case, a watchdog reset can be detected by

software while an external reset can not.

PAG

AVD

LVD

CSS

WDG

RESET Sources

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

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