ST7MC1 datasheet(64/308 Pages) STMICROELECTRONICS

部件名	ST7MC1

功能描述	8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI

PDF	308 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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64 / 308 page

ST7MC1/ST7MC2

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WINDOW WATCHDOG (Cont’d)

10.1.9 Interrupts

None.

10.1.10 Register Description

CONTROL REGISTER (WDGCR)

Read/Write

Reset Value: 0111 1111 (7Fh)

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note: This bit is not used if the hardware watch-

dog option is enabled by option byte.

Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).

These bits contain the value of the watchdog

counter. It is decremented every 16384 fOSC2 cy-

cles (approx.). A reset is produced when it rolls

over from 40h to 3Fh (T6 becomes cleared).

WINDOW REGISTER (WDGWR)

Read/Write

Reset Value: 0111 1111 (7Fh)

Bit 7 = Reserved

Bits 6:0 = W[6:0] 7-bit window value

These bits contain the window value to be com-

pared to the downcounter.

WDGA

-W6

ST7MC1 数据表(PDF) 64 Page - STMicroelectronics