ST7MC1 datasheet(27/308 Pages) STMICROELECTRONICS

27 / 308 page

ST7MC1/ST7MC2

27/308

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components. An

overview is shown in Figure 13.

For more details, refer to dedicated parametric

section.

Main features

■ Reset Sequence Manager (RSM)

■ 1 Crystal/Ceramic resonator oscillator

■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD)

– Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply

– Clock Security System (CSS) with the VCO of

the PLL, providing a backup safe oscillator

– Clock Detector

– PLL which can be used to multiply the fre-

quency by 2 if the clock frequency input is

8MHz

Figure 13. Clock, Reset and Supply Block Diagram

LOW VOLTAGE

DETECTOR

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

OSCILLATOR

OSC1

RESET

VSS

VDD

RESET SEQUENCE

MANAGER

(RSM)

CLOCK SECURITY SYSTEM

OSC2

MAIN CLOCK

CSS Interrupt Request

AVD Interrupt Request

CONTROLLER

SYSTEM

WATCHDOG

SICSR, page 0

TIMER (WDG)

WITH REALTIME

CLOCK (MCC/RTC)

AVD AVD LVD

CSS

WDG

fOSC

fCPU

fMTC

1/2

Safeosc

8Mhz PLL

Clock Detector

VCO

PLL

SICSR, page 1

16Mhz

fOSC

CKSEL

DIV2 OPT

lock

INTEGRITY MANAGEMENT

SEL

fCLK

* It is recommended to decouple the power supply by placing a 0.1µF capacitor as close as possible to VDD

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