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ST7MC1 数据表(PDF) 19 Page - STMicroelectronics |
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ST7MC1 数据表(HTML) 19 Page - STMicroelectronics |
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19 / 308 page  ST7MC1/ST7MC2 19/308 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah MTC (page 0) MTIM MTIML MZPRV MZREG MCOMP MDREG MWGHT MPRSR MIMR MISR MCRA MCRB MCRC MPHST MDFR MCFR MREF MPCR MREP MCPWH MCPWL MCPVH MCPVL MCPUH MCPUL MCP0H MCP0L Timer Counter High Register Timer Counter Low Register Capture Zn-1 Register Capture Zn Register Compare Cn+1 Register Demagnetization Register An Weight Register Prescaler & Sampling Register Interrupt Mask Register Interrupt Status Register Control Register A Control Register B Control Register C Phase State Register D event Filter Register Current feedback Filter Register Reference Register PWM Control Register Repetition Counter Register Compare Phase W Preload Register High Compare Phase W Preload Register Low Compare Phase V Preload Register High Compare Phase V Preload Register Low Compare Phase U Preload Register High Compare Phase U Preload Register Low Compare Phase 0 Preload Register High Compare Phase 0 Preload Register Low 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 0Fh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 0Fh FFh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0050h 0051h 0052h 0053h 0054h 0055h 0056h MTC (page 1) MDTG MPOL MPWME MCONF MPAR MZRF MSCR Dead Time Generator Enable Polarity Register PWM Register Configuration Register Parity Register Z event Filter Register Sampling Clock Register FFh 3Fh 00h 02h 00h 0Fh 00h see MTC description 0057h to 006Ah Reserved Area (4 Bytes) 006Bh 006Ch 006Dh 006Eh 006Fh 0070h DM DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L Debug Control Register Debug Status Register Debug Breakpoint 1 MSB Register Debug Breakpoint 1 LSB Register Debug Breakpoint 2 MSB Register Debug Breakpoint 2 LSB Register 00h 10h FFh FFh FFh FFh R/W Read Only R/W R/W R/W R/W Table 2. Hardware Register Map Address Block Register Label Register Name Reset Status Remarks 1 |
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