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ST7MC1 数据表(PDF) 35 Page - STMicroelectronics |
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ST7MC1 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 308 page ![]() ST7MC1/ST7MC2 35/308 SYSTEM INTEGRITY MANAGEMENT (Cont’d) SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 1) Reset Value: 00000000 (00h) Bit 7 = PAGE SICSR Register Page Selection This bit selects the SICSR register page. It is set and cleared by software 0: Access to SICSR register mapped in page 0. 1: Access to SICSR register mapped in page 1. Bit 6 = Reserved, must be kept cleared. Bit 5 = VCOEN VCO Enable This bit is set and cleared by software. 0: VCO (Voltage Controlled Oscillator) connected to the output of the PLL charge pump (default mode), to obtain a 16-MHz output frequency (with an 8-MHz input frequency). 1: VCO tied to ground in order to obtain a 10-MHz frequency (fvco) Notes: 1. During ICC session, this bit is set to 1 in order to have an internal frequency which does not depend on the input clock. Then, it can be reset in order to run faster with an external oscillator. Bit 4 = LOCK PLL Locked This bit is read only. It is set by hardware. It is set automatically when the PLL reaches its operating frequency. 0: PLL not locked 1: PLL locked Bit 3 = PLLEN PLL Enable This bit enables the PLL and the clock detector. It is set and cleared by software. 0: PLL and Clock Detector (CKD) disabled 1: PLL and Clock Detector (CKD) enabled Notes: 1. During ICC session, this bit is set to 1. 2. PLL cannot be disabled if PLL clock source is selected (CKSEL= 1). Bit 2 = Reserved, must be kept cleared. Bit 1 = CKSEL Clock Source Selection This bit selects the clock source: oscillator clock or clock from the PLL. It is set and cleared by soft- ware. It can also be set by option byte (PLL opt) 0: Oscillator clock selected 1: PLL clock selected Notes: 1. During ICC session, this bit is set to 1. Then, CKSEL can be reset in order to run with fOSC. 2. Clock from the PLL cannot be selected if the PLL is disabled (PLLEN =0) 3. If the clock source is selected by PLL option bit, CKSEL bit selection has no effect. Bit 0 = Reserved, must be kept cleared. 70 PA GE 0 VCO EN LO CK PLL EN 0 CK- SEL 0 1 |
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