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ST7MC1 数据表(PDF) 238 Page - STMicroelectronics |
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ST7MC1 数据表(HTML) 238 Page - STMicroelectronics |
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238 / 308 page  ST7MC1/ST7MC2 238/308 10-BIT A/D CONVERTER (ADC) (Cont’d) 10.8.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by soft- ware reading the ADCDRMSB register. 0: Conversion is not complete 1: Conversion complete Bit 6:5 = PRSC[1:0] ADC clock prescaler selection These bits are set and cleared by software. Bit 4 = ADON A/D Converter on This bit is set and cleared by software. 0: Disable ADC and stop conversion 1: Enable ADC and start conversion Bit 3:0 = CS[3:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert. *The number of channels is device dependent. Refer to the device pinout description. DATA REGISTER (ADCDRMSB) Read Only Reset Value: 0000 0000 (00h) Bit 7:0 = D[9:2] MSB of Analog Converted Value This register contains the MSB of the converted analog value. DATA REGISTER (ADCDRLSB) Read Only Reset Value: 0000 0000 (00h) Bit 7:2 = Reserved. Forced by hardware to 0. Bit 1:0 = D[1:0] LSB of Analog Converted Value This register contains the LSB of the converted an- alog value. 70 EOC PRSC1 PRSC0 ADON CS3 CS2 CS1 CS0 fADC PRSC1 PRSC0 4MHz 0 0 2MHz 0 1 1MHz 1 0 Channel Pin* CH3 CH2 CH1 CH0 AIN0 0 000 AIN1 0 001 AIN2 0 010 AIN3 0 011 AIN4 0 100 AIN5 0 101 AIN6 0 110 AIN7 0 111 AIN8 1 000 AIN9 1 001 AIN10 1 010 AIN11 1 011 AIN12 1 100 AIN13 1 101 AIN14 1 110 AIN15 1 111 70 D9 D8 D7 D6 D5 D4 D3 D2 70 0 000 00 D1 D0 |
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