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STLUX 数据表(PDF) 71 Page - STMicroelectronics

部件名 STLUX
功能描述  Digital controllers for lighting and power conversion applications with up to 6 programmable PWM generators, 96 MHz PLL, DALI
PDF  126 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLUX 数据表(HTML) 71 Page - STMicroelectronics

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STLUX
Option bytes
126
nGENCFG (general configuration register protection)
nGENCFG: not (GENCFG) EMC byte protection.
MISCUOPT (miscellaneous configuration register)
Bit 0:
WWdg_HALT window watchdog reset on Halt: 0: no reset generated on Halt if WWDG
is active 1: reset generated on Halt if WWDG is active.
Bit 1:
WWdg_hw window watchdog hardware enable: 0: window watchdog activation by SW
1: window watchdog activation by HW. Bit 2:
IWdg_hw independent watchdog hardware enable:
0: independent watchdog activation by SW 1: independent watchdog activation by HW.
Bit 3:
LSI_EN low speed internal RCOSC clock enable:
0: LSI clock is not available to CPU
1: LSI cock is enabled for CPU.
Bit 4:
RFU reserved; must be kept 0 during register writing for future compatibility.
Bit 5:
RFU reserved; must be kept 1 during register writing for future compatibility.
Bit 7 - 6:
RFU reserved; must be kept 0 during register writing for future compatibility.
Table 45. nGENCFG (general configuration register protection)
Offset: 0x004804
Default value: 0xFF
7
6
543
2
1
0
nRst_PWM [5:0]
nCOMP1_2
nEN_COLD_CFG
r/w
r/w
r/w
Table 46. MISCUOPT (miscellaneous configuration register)
Offset: 0x004805
Default value: 0x28 (factory configuration)
76
5
4
3
2
1
0
RFU
RFU
RFU
LSI_EN
lWdg_hw
WWdg_hw
WWDG_HALT
r
r
r
r/w
r/w
r/w
r/w



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