STLUX datasheet(38/126 Pages) STMICROELECTRONICS

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I/O multifunction signal configuration

STLUX

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DocID027870 Rev 1

7.3

Port P1 I/O multifunction configuration signal

The Port P1 I/O multifunction pins, similarly to the Port P0, can be individually configured

through the following set of registers based on the selected device configuration policy:



Cold configuration: AFR_IOMXP1 option byte register (refer to Section 10 on page 60).

After reset the P1 signals are configured in line with AFR_IOMXP1 contents.



Warm configuration: MSC_IOMXP1 miscellaneous register (refer to Section 7.5). After

reset the P1 signals are configured as PWM output lines.

Every Port1 I/O can be configured to operate as a PWM output pin or a GPIO. Differently

from the port P0s, the pins are configured as PWM output signals by default after reset.

Table 7 summarizes the Port P1 configurations as selected by the register fields Sel_p15 …

Sel_p10 which respectively control the bits [5] … [0] of the Port P1 (verify resources

availability in Table 4 on page 32).

Table 7. Port P1 I/O multiplexing signal(1)

1. The Sel_p15…Sel_p10 are common register fields of both registers MSC_IOMXP1 and AFR_IOMXP1.

In cold configuration the P1x are configured as defined by the AFR_IOMXP1 option byte.

The PWM default polarity level is configured by the register option byte GENCFG.

Verify pin availability in Table 4 on page 32.

Port P1 multifunction configuration signal

Output signal

Multifunction signal

MUX selection

Selection bits

Value (binary)

P1[0]

PWM[0]

Sel_P10

GPIO1[0]

P1[1]

PWM[1]

Sel_P11

GPIO1[1]

P1[2]

PWM[2]

Sel_P12

GPIO1[2]

P1[3]

PWM[3]

Sel_P13

GPIO1[3]

P1[4]

PWM[4]

Sel_P14

GPIO1[4]

P1[5]

PWM[5]

Sel_P15

GPIO1[5]

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