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STLUX 数据表(PDF) 91 Page - STMicroelectronics |
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STLUX 数据表(HTML) 91 Page - STMicroelectronics |
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91 / 126 page ![]() DocID027870 Rev 1 91/126 STLUX Electrical characteristics 126 IDD(PWM1HSI8) Enab 8 0.5 0 Disab 1 Disab 0.4 0.5 IDD(PWM4HSI8) 4 1.39 1.7 IDD(PWM5HSI8) 5 1.95 2.4 IDD(PWM6HSI8) 6 2.12 2.55 IDD(PWM1HSI4) Enab 4 0.5 0 Disab 1 Disab 0.3 0.4 IDD(PWM4HSI4) 4 1.21 1.48 IDD(PWM5HSI4) 51.7 2.2 IDD(PWM6HSI4) 6 1.78 2.2 IDD(PWM1HSI2) Enab 2 0.5 0 Disab 1 Disab 0.25 0.3 IDD(PWM4HSI2) 4 1.07 1.31 IDD(PWM5HSI2) 5 1.52 1.9 IDD(PWM6HSI2) 6 1.60 1.93 IDD(ADC1) Disab 0 0 1 Enab 0 Disab 1.55 1.87 IDD(ADC2) Disab 0 0 5.3 Enab 0 Disab 1.6 1.95 IDD(ADC3) Enab 0 0 6 Enab 0 Disab 1.56 1.88 1. Data based on characterization results not tested in production. 2. SMED frequency: - 96 MHz and 6 MHz frequencies require the PLL enabled. - Current table shows only a subset value of possible SMED frequencies. 3. PWM frequency: - PWM toggle frequency is considered fixed to 500 kHz, close to the maximum applicative value. 4. 3.ADC frequency: - 6 MHz frequency requires the PLL enabled. - Current table shows only a subset value of possible ADC frequencies. 5. ADC configured in circular mode. 6. PWM pins are loaded with a CL (load capacitance) of 50 pF. 7. Number of active PWMs. 8. If enabled all DACs and comparator units are active. 9. Temperature operating: TA = 25 °C. Table 74. Peripheral supply current consumption at VDD/VDDA = 3.3 V (continued) Symbol Clock Peripherals Consumption(1) |
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