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STLUX

I/O multifunction signal configuration

126

I/O multifunction signal configuration

Several I/Os have multiple functionalities selectable through the configuration mechanism

described from Section 7.1 to Section 7.5 on page 41. The STLUX I/Os are grouped into

four different configurable ports: P0, P1, P2 and P3.

7.1

Multifunction configuration policy

The STLUX supports either a cold or warm multifunction signal configuration policy

according to the content of the EN_COLD_CFG bit field, a part of the GENCFG option byte

When the EN_COLD_CFG bit is set, the cold configuration is selected and the multifunction

signals are configured according to the values stored in the option bytes; otherwise when

the EN_COLD_CFG bit is cleared (default case), the warm configuration mode is chosen

and the multifunction pin functionality is configured through the miscellaneous registers.

The configuration options and the proper configuration registers are detailed in Table 5:

The warm configuration is volatile, thus not maintained after a device reset.

7.2

Port P0 I/O multifunction configuration signal

The Port P0 multiplexes several input/output functionalities, increasing the device flexibility.

The P0 port pins can be independently assigned to general purpose I/Os or to internal

peripherals. All communication peripherals and the external oscillator are hosted by the Port

P0 pins.

In order to avoid electrical conflicts on the user application board, the P0 signals are

configured at reset as GPIO0 inputs without pull-up resistors. Once the reset is released,

the firmware application must initialize the inputs with the proper configuration according to

the application needs.

7.2.1

Alternate function P0 configuration signals

The multifunction pins can be configured via one of the following two registers, depending

on the overall configuration policy (warm/cold):



Cold configuration: AFR_IOMXP0 option byte registers (refer to Section 10: Option

bytes on page 60). After the reset the P0 signals are configured in line with

AFR_IOMXP0 contents.



Warm configuration: MSC_IOMXP0 miscellaneous register (refer to Section 7.5 on

page 41). After the reset, the P0 signals are configured as GPIO input lines with the

pull-up disabled.

Table 5. Multifunction configuration registers

EN_COLD_CFG Configuration policy

Multifunction configuration registers

Cold

AFR_IOMXP0, AFR_IOMXP1 and AFR_IOMXP2

0 (default)

Warm

MSC_IOMXP0, MSC_IOMXP1 and MSC_IOMXP2

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