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数据搜索系统，热门电子元器件搜索 |
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STLUX 数据表(PDF) 74 Page - STMicroelectronics |
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STLUX 数据表(HTML) 74 Page - STMicroelectronics |
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74 / 126 page  Option bytes STLUX 74/126 DocID027870 Rev 1 WAITSTATE (Flash wait state register) Bit 1 - 0: WaitStat [1:0] configures the E²PROM and Flash programmable delay read access time: 00: 0 no delay cycle (default case fMASTER at 16 MHz) 01: 1 delay cycles 10: 2 delay cycles 11: 3 delay cycles. Bit 7 - 2: RFU reserved; must be kept 0 during register writing for future compatibility. nWAITSTATE (Flash wait state register protection) nWAITSTATE: not (WAITSTATE) EMC byte protection. Table 52. WAITSTATE (Flash wait state register) Offset: 0x00480D Default value: 0x00 or 0x40 according to the device 7 6 5 432 1 0 RFU WaitStat [1:0] rr/w Table 53. nWAITSTATE (Flash wait state register) Offset: 0x00480E Default value: 0xFF or BF according to the device 7 6 54 32 1 0 nRFU nWaitStat [1:0] rr/w |
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