STLUX datasheet(24/126 Pages) STMICROELECTRONICS

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Product overview

STLUX

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DocID027870 Rev 1

5.4.4

Readout protection (ROP)

The STLUX family provides a readout protection of the code and data memory which can be

activated by an option byte setting.

The readout protection prevents reading and writing program memory, data memory and

option bytes via the debug module and SWIM interface. This protection is active in all device

operation modes. Any attempt to remove the protection by overwriting the ROP option byte

triggers a global erase of the program and data memory contents.

5.5

Clock controller

The clock controller distributes the system clock provided by different oscillators to the core

and the peripherals. It also manages clock gating for low power modes and ensures clock

robustness.

The main clock controller features are:



Clock sources



Internal 16-MHz and 153.6-kHz RC oscillators



External source clock:

–

Crystal/resonator oscillator

–

External clock input



Internal PLL at 96 MHz (not used as the fMASTER source clock)



Reset: after the reset the microcontroller restarts by default with the HSI internal clock

scaled at 2 MHz (16 MHz/8). The clock source and speed can be changed by the

application program as soon as the code execution starts.



Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register. The clock signal is not switched until the new clock

source is ready. The design guarantees glitch-free switching.



Clock management: to reduce power consumption, the clock controller can stop the

clock to the core or individual peripherals.



Wakeup: in case the device wakes up from low power modes, the internal RC oscillator

(16 MHz/8) is used for a quick startup. After a stabilization time, the device brings back

the clock source that was selected before Halt mode was entered.



Clock security system (CSS): the CSS permits monitoring of external clock sources

and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.



Configurable main clock output (CCO): this feature permits to output an internal clock

source signal for application usage.

5.5.1

Internal 16 MHz RC oscillator (HSI)

The high speed internal (HSI) clock is the default master clock line, generated by an internal

RC oscillator and with nominal frequency of 16 MHz. It has the following major features:



RC architecture



Glitch-free oscillation



3-bit user calibration circuit.

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