STLUX datasheet(40/126 Pages) STMICROELECTRONICS

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I/O multifunction signal configuration

STLUX

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DocID027870 Rev 1

Note:

The Sel_P254 is a common register field of both registers MSC_IOMXP2 and

AFR_IOMXP2.

The peripheral conflict (same resources selected on different pins at the same time) has to

be prevented by SW configuration.

The signal ports P2 [3:1] are exclusively interconnected with DIGIN [3:1] primary pins. When

the I2C i/f is selected on DIGIN [5:4] signals the I/O speed is auto-configured at 10 MHz and

the internal pull-up functionality is controlled by the MSC_INPP2AUX1 register.

The GPIO0 [6] signal is selected when both Sel_SWIM = '0' and CFG_GCR [0] = '1'.

SWIM signal function is selected when the CFG_GCR [0] = '0'.

After reset by default the P2 [0] is configured as the DIGIN [0] signal.

Verify pinout availability in Table 4: Pin description on page 32.

The P2 [0] is configured by the CCOEN field of the CKC_CCOR register as shown in

Table 8.

7.4.1

P2 interrupt capability

Port P2 signals may be configured to generate maskable (IRQ) and un-maskable (NMI)

interrupts by configuring the MSC_CFGP2<n> and the MSC_STSP2 registers (n = index

port signal 0-5).

The interrupt request may be configured to wake-up the IC device from the WFI (wait for

interrupt), AHalt (active Halt) and Halt power saving state.

7.4.2

P2 programmable pull-up feature

The pad pull-up resistances (47 k

) of Port2 signals are individually controllable by the

MSC_INPP2AUX1 register.

Table 8. Port P2 I/O multiplexing signal

Port P2 multifunction configuration signal

Output signal

Multifunction signal

MUX selection

Selection bits

Value (binary)

P2[0]

DIGIN[0]

CCOEN

CCO

P2[4]

DIGIN[4]

Sel_P254

I2C_sda

P2[5]

DIGIN[5]

Sel_P254

I2C_scl

SWIM

GPIO0[6]

Sel_SWIM

SWIM

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