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STLUX 数据表(PDF) 50 Page - STMicroelectronics |
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STLUX 数据表(HTML) 50 Page - STMicroelectronics |
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50 / 126 page  Memory and register map STLUX 50/126 DocID027870 Rev 1 8.2.6 Clock and clock controller Table 20. Clock and clock controller register map Address Block Register name Register description 0x00.50B4 CKC CLK_SMD0 SMED 0 clock configuration 0x00.50B5 CLK_SMD1 SMED 1 clock configuration 0x00.50B6 CLK_SMD2 SMED 2 clock configuration 0x00.50B7 CLK_SMD3 SMED 3 clock configuration 0x00.50B8 CLK_SMD4 SMED 4 clock configuration 0x00.50B9 CLK_SMD5 SMED 5 clock configuration 0x00.50BA RFU Reserved for future use 0x00.50BB RFU Reserved for future use 0x00.50BC RFU Reserved for future use 0x00.50BD RFU Reserved for future use 0x00.50BE CLK_PLLDIV PLL clock divisor 0x00.50BF CLK_AWUDIV AWU clock divisor 0x00.50C0 CLK_ICKR Internal clock control 0x00.50C1 CLK_ECKR External clock control 0x00.50C2 CLK_PLLR PLL control 0x00.50C3 CLK_CMSR Clock master 0x00.50C4 CLK_SWR Clock switch 0x00.50C5 CLK_SWCR Switch control 0x00.50C6 CLK_CKDIVR Clock dividers 0x00.50C7 CLK_PCKENR1 Peripherals clock enable 0x00.50C8 CLK_CSSR Clock security system 0x00.50C9 CLK_CCOR Configurable clock output 0x00.50CA CLK_PCKENR2 Peripherals clock enable 0x00.50CB RFU Reserved for future use 0x00.50CC CLK_HSITRIMR HSI calibration trimmer 0x00.50CD CLK_SWIMCCR SWIM clock division 0x00.50CE CLK_CCODIVR CCO divider 0x00.50CF CLK_ADCR ADC clock configuration |
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