STLUX datasheet(41/126 Pages) STMICROELECTRONICS

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STLUX

I/O multifunction signal configuration

126

7.5

Multifunction Port configuration registers

MSC_IOMXP0 (Port P1 I/O MUX control register)

The Port0 I/O multifunction signal configurations register (for functionality description refer

to Section 7.2 on page 35).

Verify pinout availability in Table 4: Pin description on page 32.

Bit 1 - 0:

Sel_P010 [1:0] Port0 [1:0] I/O multiplexing scheme:

00: Port0 [1:0] are interconnected to GPIO0 [1:0] signals

01: Port0 [1:0] are interconnected to UART_rx and UART_tx signals

10: Port0 [1:0] are interconnected to I2C_scl and I2C_sda signals

11: RFU

Bit 3 - 2:

Sel_P032 [1:0] Port0 [3:2] I/O multiplexing scheme:

00: Port0 [3:2] are interconnected to GPIO0 [3:2] signals

01: Port0 [3:2] are interconnected to I2C_scl and I2C_sda signals

10: Port0 [3:2] are interconnected to HseOscin and HseOscout analog signals

11: Port0 [3:2] are interconnected to UART_rx and UART_tx signals

Bit 5 - 4:

Sel_P054 [1:0] Port0 [5:4] I/O multiplexing scheme:

00: Port0 [5:4] are interconnected to GPIO0 [5:4] signals

01: Port0 [5:4] are interconnected to DALI_rx and DALI_tx signals

10: Port0 [5:4] are interconnected to I2C_scl and I2C_sda signals

11: Port0 [5:4] are interconnected to UART_rx and UART_tx signals

Bit 7 - 6:

RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0

during register write operations.

Table 9. MSC_IOMXP0 (Port P1 I/O MUX control register)

Offset: 0x2A

Default value: 0x00

65432

RFU

Sel_P054 [1:0]

Sel_P032 [1:0]

Sel_P010 [1:0](1)

1. Not available on the STLUX325A and STLUX285A.

rr/w

r/w

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