S2-LP datasheet(65/90 Pages) STMICROELECTRONICS

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S2-LP

Link layer protocol

DocID029944 Rev 1

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LDC_RELOAD_PRESCALER and LDC_COUNTER registers. In so doing, the

counting can be delayed or anticipated.



Only for the RX device, the wake-up timer can be automatically reloaded at the time

the SYNC is received. This option must be enabled on the PROTOCOL register.

The estimation of the values to be reloaded in order to get optimal LDC phasing is in

charge of the MCU, which should be synchronized with the S2-LP RCO using any of the

available clock outputs.

The details about LDC operation for the RX device are the following:

The starting state is READY: as soon as user sets the LDC_MODE bit, LDC counter

starts in free running mode.

The first RX operation is triggered by the RX command.

First RX should be executed with a long (or infinite) timeout (LDC counter is still free

running, not synchronized).

After first RX, the user should synchronize the LDC counter by using the

LDC_RELOAD command.

Synchronization could be automatically triggered by the detection of the SYNC word.

After each RX, the state machine will operate as follows:

If no pending interrupt (nIRQ=1), then automatically go to SLEEP for LDC, but

only after RCCAL_OK goes to 1 (RCO calibration complete).

If any pending interrupt (nIRQ=0), then stay in READY (MCU will send a SLEEP

command to go in SLEEP and resume LDC operation).

If FIFOs are not retained in SLEEP, then the MCU must read the RX FIFO during the

READY state, before giving the SLEEP command.

When the LDC_MODE bit is reset, the LDC counters will continue to decrement and,

when the device awakes from SLEEP, the LDC cycling will be stopped and the device

remain in READY.

The details about LDC operation for the TX device are the following:

The starting state is READY: as soon as user sets the LDC_MODE bit, LDC counter

starts in free running mode.

The first TX operation is triggered by the TX command.

First TX is executed always (even if TX FIFO is empty); the next will happen only if TX

FIFO is not empty.

At first TX, the LDC counter will automatically be reloaded.

If TX FIFO is empty, the current slot will be skipped and the device will remain in

SLEEP state.

The TX FIFO can be written during the SLEEP state also.

When the LDC_MODE bit is reset, the LDC counter will continue to decrement and,

when the device awakes from SLEEP, the LDC cycling will be stopped and the device

remain in READY. However, it is also true that:

In case the TX FIFO is empty, the device will still remain in SLEEP state until the

FIFO is written or a READY command is provided.

In case the TX FIFO is not empty, a last TX operation will be performed before

the LDC stops.

For the Tx, the bit SLEEP_MODE_SEL should be set to 1, selecting the SLEEP_B mode.

In this way, the TX_FIFO can be written in SLEEP.

8.2.1.1

Automatic acknowledgment

The LDC mode can be used together with the automatic acknowledgment. In this case

during a single LDC cycle both the operations of reception and transmission are performed.

In case of TX, the device will wake up every WAKE-UP time and switch to RX for the

RX_TIMEOUT set waiting for an ack.

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