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S2-LP 数据表(PDF) 82 Page - STMicroelectronics |
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S2-LP 数据表(HTML) 82 Page - STMicroelectronics |
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82 / 90 page ![]() Register contents S2-LP 82/90 DocID029944 Rev 1 Name Addr Default Bit Field name Description 6:0 PA_LEVEL8 Output power level for 8th slot. PA_POWER7 5B 0C 7 RESERVED - 6:0 PA_LEVEL_7 Output power level for 7th slot. PA_POWER6 5C 18 7 RESERVED - 6:0 PA_LEVEL_6 Output power level for 6th slot. PA_POWER5 5D 24 7 RESERVED - 6:0 PA_LEVEL_5 Output power level for 5th slot. PA_POWER4 5E 30 7 RESERVED - 6:0 PA_LEVEL_4 Output power level for 4th slot. PA_POWER3 5F 48 7 RESERVED - 6:0 PA_LEVEL_3 Output power level for 3rd slot. PA_POWER2 60 60 7 RESERVED - 6:0 PA_LEVEL_2 Output power level for 2nd slot. PA_POWER1 61 00 7 RESERVED - 6:0 PA_LEVEL_1 Output power level for 1st slot. PA_POWER0 62 47 7 DIG_SMOOTH_EN 1: enable the generation of the internal signal TX_DATA which is the input of the FIR. Needed when FIR_EN=1. 6 PA_MAXDBM 1: configure the PA to send maximum output power. 5 PA_RAMP_EN 1: enable the power ramping 4:3 PA_RAMP_STEP_LEN Set the step width (unit: 1/8 of bit period). 2:0 PA_LEVEL_MAX_IDX Final level for power ramping or selected output power index. PA_CONFIG1 63 03 7:4 RESERVED - 3:2 FIR_CFG FIR configuration: 00b: filtering 01b: ramping 10b: switching (see Section 5.4.2.1) 1 FIR_EN 1: enable FIR (see Section 5.4.2.1) 0 RESERVED - PA_CONFIG0 64 8A 7:2 RESERVED - 1:0 PA_FC PA Bessel filter bandwidth: 00b: 12.5kHz (data rate 16.2kbps) 01b: 25kHz (data rate 32kbps) 10b: 50kHz (data rate 62.5kbps) 11b: 100kHz (data rate 125kbps) see Section 5.4.2.1 SYNTH_CONFIG2 65 D0 7:3 RESERVED - 2 PLL_PFD_SPLIT_EN Enables increased DN current pulses to improve linearization of CP/PFD (see Table 34). 1:0 RESERVED - VCO_CONFIG 68 03 7:6 RESERVED - 5 VCO_CALAMP_EXT_SEL 1 → VCO amplitude calibration will be skipped (external amplitude word forced on VCO). 4 VCO_CALFREQ_EXT_SEL 1 → VCO frequency calibration will be skipped (external amplitude word forced on VCO). 3:0 RESERVED - |
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