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S2-LP 数据表(PDF) 25 Page - STMicroelectronics

部件名 S2-LP
功能描述  Excellent receiver selectivity and blocking
PDF  90 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

S2-LP 数据表(HTML) 25 Page - STMicroelectronics

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S2-LP
Specifications
DocID029944 Rev 1
25/90
4.9.3
Harmonic emission at 915 MHz
Table 29: Harmonic emission at 915 MHz
Parameter
Test conditions
SMPS on
Unit
H1
CW
14
dBm
H2
CW
-46
H3
CW
-55
H4
CW
-46
H5
CW
-49
H6
CW
-48
H7
CW
-51
4.10
Digital interface specification
Table 30: Digital SPI input, output and GPIO specification
Parameter
Test condition
Min.
Typ.
Max.
Unit
SPI clock frequency
8
10
MHz
Port I/O capacitance
1.4
pF
Rise time
From 0.1*VDD to 0.9*VDD, CL=20
pF (low output current
programming)
6.0
ns
From 0.1*VDD to 0.9*VDD, CL=20
pF (high output current
programming)
2.5
Fall time
From 0.1*VDD to 0.9*VDD, CL=20
pF (low output current
programming)
7.0
ns
From 0.1*VDD to 0.9*VDD, CL=20
pF (high output current
programming)
2.5
Logic high level input
voltage
VDD/2
+0.3
V
Logic low level input
voltage
VDD/8
+0.3
V
High level output voltage
IOH = -2.4 mA (-4.2 mA into high
output current mode).
(5/8)*
VDD+
0.1
V
Low level output voltage
IOL = +2.0 mA (+4.0 mA into high
output current mode).
0.5
V
CSn low to positive edge
on SCLK in ready state
40
µs



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