S2-LP datasheet(36/90 Pages) STMICROELECTRONICS

36 / 90 page

Block description

S2-LP

36/90

DocID029944 Rev 1

�� =

{

�� ·

��_��

232

��_�� = 0

�� ·

(216 + ��_��) ∙ 2��_��

233

��_�� > 0

��

8 ∙ ��_��

��_�� = 15

where

�� is the digital clock frequency.

In the cases where DATARATE_E<15, the actual modulator timing is generated by a

fractional clock divider hence is affected by a certain amount of jitter. In order to have a

jitter free data rate generation a specific mode the last equation must be used,

DATARATE_E = 15 (only for transmission).

5.5

Receiver

The S2-LP contains a low-power low-IF receiver able to amplify the input signal and

provide it to the ADC with a proper signal to noise ratio. The RF antenna signal is

converted to a differential one by an external balun, which performs an impedance

transformation also. The receiver gain can be programmed to accommodate the ADC input

signal within its dynamic range. After the down-conversion at IF, a first order filter is

implemented to attenuate the out-of-band blockers.

5.5.1

Automatic frequency compensation

The Automatic Frequency Compensation (AFC for short) algorithm allows compensating,

within certain limits, a relative frequency error between the transmitting device and the

receiving one caused by for example from crystal inaccuracies.

The AFC algorithm is operational only for frequency modulation such as 2-(G)FSK and 4-

(G)FSK.

Due to the demodulation algorithm employed, any frequency error results in a DC offset in

the demodulated signal before slicing.

The basic operating principle of the AFC is that the minimum and maximum signal

frequencies are detected and a correction is calculated to remove the aforementioned

offset.

Such correction is either applied at the slicer level in the form of offset compensation

(default mode) or, optionally, is used to adjust the second IF conversion stage frequency.

The former mode allows a quick recovery of the frequency error but does not prevent part

of the received signal power to be cut by the channel filter; the latter mode adjusts the

signal frequency before entering the channel filter thus avoiding power loss but requires a

longer period to settle. The first mode is recommended for normal operation.

The AFC also provides the estimated frequency error through the AFC_CORR register. If

the frequency error is known to be constant (for example communication always occurs

between the same pair of devices), this value can directly be used to correct the

programmed center frequency.

In order to guarantee both fast lock and smooth tracking, the AFC has a fast mode and a

slow mode. The AFC will start in fast mode as soon as the RSSI threshold is passed and

will switch to the slow mode after a programmable period.

The AFC is controlled by the following parameters:



RSSI threshold: this parameter sets the minimum signal power above which the AFC

algorithm is started (RSSI_TH register).

S2-LP 数据表(PDF) 36 Page - STMicroelectronics

S2-LP 数据表(HTML) 36 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表下载