S2-LP datasheet(33/90 Pages) STMICROELECTRONICS

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S2-LP

Block description

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5.4.1.2

ISI cancellation 4-(G)FSK

Since the 4-(G)FSK modulation format strongly suffers from the effect of inter symbol

interference, an ISI cancellation equalizer has been introduced in the demodulator. An

equalizer can be enabled, by using the EQU_CTRL register, with two modes: single pass

equalization and dual pass equalization. Best performances are normally achieved using

the dual pass equalizer.

5.4.2

Amplitude modulation

Amplitude modulation OOK and ASK are both supported by the S2-LP. The ASK selection

depends on power ramping enable.

When OOK is selected, a bit '1' is transmitted with a programmed power, set by register

PA_POWER[PA_LEVEL_MAX_INDEX], and a bit '0' is transmitted with the lowest power

programmed, normally set no output power (PA off) and specified by the register

PA_POWER[0].

In case PA_POWER[0] = 0 then the modulation will be OOK, otherwise when

PA_POWER[0] is not set to zero the modulation will be ASK. The 0/1 mapping can be

reversed by setting the CONST_MAP register to any value other than zero.

When ASK is selected, a bit '1' is transmitted with a power ramp increasing from the

minimum value specified by register PA_POWER[0] to specified PA maximum level in

each power step is a multiple of 1/8 of the symbol time, configurable with the register

PA_RAMP_STEP_WIDTH. If more '1's are transmitted consecutively, the PA power

maintains the output power at the programmed value. If more '0's are transmitted

consecutively, the PA power remains at minimum power for all '0's following the first one.

In order to improve the spectral emission mask is ASK a digital interpolation optional

features have been implemented. When this feature is enabled, thought the register

PA_INTERP_EN, the modulator linearly interpolates the power values specified in the

PA_POWER registers before being applied to the PA.

The interpolation factor of each ramp step is 64 time the data rate corresponding to

DATA_RATE_E < 5 it is automatically scaled as 64/2(DATA_RATE_E-5)

for 5 ≤ DATA_RATE_E <

11 and it is automatically disabled for DATA_RATE_E=11.

Note that the number of clock cycles between successive PA ticks, for DATA_RATE_E≥5,

is always between 8 and 4 (8 for DATA_RATE_M=0; 4 for DATA_RATE_M=65535).

OOK/ASK demodulation is controlled by the OOK_PEAK_DECAY parameter in the

RSSI_FLT register.

5.4.2.1

OOK smoothing

The OOK can be smoothed using a FIR filter added in the data path. This feature is

activated by setting the FIR_EN bit at 1 inside register PA_CONFIG1.

The FIR filter is not fully customizable but it can be set in 3 different configurations that

change the spectrum shape (and thus the bandwidth):



filter: it is the proper FIR filtering function of the stream of bits 8 times oversampled;



ramp: the FIR filter is optimized to perform a ramping between PA_POWER_MAX and

PA_POWER_0 (for OOK should be set to 0).



switch: logic 1s and 0s are associated with a single value of power and no transition

between the 2 is envisaged.

When the FIR_EN bit is 1, the DIG_SMOOTH_EN (PA_POWER_0 register) must be set to

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