S2-LP datasheet(71/90 Pages) STMICROELECTRONICS

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S2-LP

MCU interface

DocID029944 Rev 1

71/90

MCU interface

Communication with the MCU goes through a standard 4 wires SPI interface and 4 GPIOs

(plus SHUTDOWN pin).

MCU can performs the following operations:



Program the S2-LP in different operating modes by sending commands



Read data from the RX FIFO and write data into the TX FIFO



Configure the S2-LP through the registers



Retrieve information from the S2-LP



Get interrupt requests and signals from the GPIO pins



Apply external signals to the GPIO pins



Put the S2-LP in SHUTDOWN state or exit from SHUTDOWN state.

9.1

Serial Peripheral Interface

The four wires SPI interface consist of:



SCLK: the SPI clock from MCU to S2-LP



MOSI: data from MCU to the S2-LP



MISO: data from the S2-LP to MCU



CSn: chip select signal, active low.

As the MCU is the master, it always drives the CSn and SCLK. According to the active

SCLK polarity and phase, the S2-LP SPI can be classified as mode 1 (CPOL=0, CPHA=0),

which means that the base value of SCLK is zero, data are read on the clock's rising edge

and data are changed on the clock's falling edge. The MISO is in tri-state mode when CSn

is high. All transfers are MSB first.

The interface allows the following operations:



Write data (to registers or TX FIFO)



Read data (from registers or RX FIFO)



Send commands.

The SPI communication is supported in all the active states, and also during the low power

state: STANDBY and SLEEP.

When accessing the SPI interface, the two status bytes of the MC_STATE registers are

sent to the MISO pin.

Figure 24: SPI write sequence

SCLK

(CPOL =0)

CSn

MOSI

Header Byte

Data written to Address

Data written to Address+1

MISO

W/R

A/C

Don

’t Care

Tri-State

Spirit1 Memory Map Address

S15

S14

S13

S12

S11

S10

Spirit1 Status bits

(CPHA =0)

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