S2-LP datasheet(72/90 Pages) STMICROELECTRONICS

72 / 90 page

MCU interface

S2-LP

72/90

DocID029944 Rev 1

Figure 25: SPI read sequence

Figure 26: SPI command sequence

Concerning the first byte, the MSB is an A/C bit (Address/Commands: 0 indicates that the

following byte is an address, 1 indicates that the following byte is a command code), while

the LSB is a W/R bit (Write/Read: 1 indicates a read operation). All other bits must be zero.

Read and write operations are persistently executed while CSn is kept active (low), the

address is automatically incremented (burst mode).

Accessing the FIFO is done as usual with the read and write commands, by putting, as

address, the code 0xFF. Burst mode is available to access the sequence of bytes in the

FIFO. Clearly, RX-FIFO is accessed with a read operation, TX-FIFO with a write operation.

9.2

Interrupts

In order to notify the MCU of a certain number of events an interrupt signal is generated on

a selectable GPIO. The following events trigger an interrupt to the MCU:

Table 56: Interrupts list

Bit

Events group

Interrupt event

Packet oriented

RX data ready

RX data discarded (upon filtering)

TX data sent

Max. re-TX reached

SCLK

CSn

MOSI

Header Byte

W/R

A/C

Don

’t Care

Tri-State

Spirit1 Command Code

MISO

S15

S14

S13

S12

S11

S10

Spirit1 Status bits

SCLK

CSn

MOSI

Header Byte

W/R

A/C

Don

’t Care

Tri-State

Spirit1 Command Code

MISO

S15

S14

S13

S12

S11

S10

Spirit1 Status bits

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