S2-LP datasheet(37/90 Pages) STMICROELECTRONICS

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S2-LP

Block description

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

AFC fast gain log2: this parameter sets the loop gain in the fast mode (AFC0 register),

the range allowed is 0..15.



AFC slow gain log2: this parameter sets the loop gain in the slow mode (AFC0



AFC fast period: this parameter sets the length of the fast period in number of samples

(AFC1 register), the range allowed is 0...255. The recommended setting for this

parameter is such that the fast period equals the preamble length. Since the algorithm

operates typically on 2 samples per symbol, the programmed value should be twice

the number of preamble symbols. If this parameter is set to 0 then the switching from

fast to slow mode is controlled by the sync word detection, for example the fast gain is

used before the sync detection, the slow gain is used after sync detection.



AFC peak detection leakage: this parameter sets the decay speed of the min/max

frequency peak detector (AFC2 register), the range allowed is 0...31 (0: no leakage,

31: high leakage). The recommended value for this parameter is 4.



AFC mode: this parameter sets the AFC correction mode (AFC2 register. 0b: slicer

correction, 1b: 2nd IF correction).



AFC enable: this parameter enables the AFC algorithm (AFC2 register).



AFC init mode: (AFC_INIT_MODE register) this parameter controls the initialization

phase of the AGC and clock recovery algorithms.



When AFC_init_mode = 0, the initial frequency error is estimated based on the

average of the frequency deviation of the first 4 received symbols after that the

RSSI has passed the threshold level.



When AFC_init_mode = 1, the initial frequency error is estimated based on the

max/min frequency deviation detected during the synchronization word and the

clock recovery algorithm is initialized based on the zero crossing points of the last

4 preamble symbols. This mode provides better performance in case of packet

formats with very short preamble.

5.5.2

Automatic gain control

The Automatic Gain Control (AGC for short) algorithm is designed to keep the signal

amplitude at the input of the IF ADC within a specific range by controlling the gain of the RF

chain in 6 dB steps, up to a maximum attenuation of 48 dB, starting at a received signal

power of about -50 dBm.

From an implementation point of view, the (peak) signal amplitude is measured in the

digital domain after the primary decimation filters chain and compared to a low threshold

and to a high threshold. If the amplitude is above the high threshold, the attenuation is

increased sequentially until the amplitude goes below the threshold; if the amplitude is

below the low threshold, the attenuation is decreased sequentially until the amplitude goes

above the threshold.

The AGC algorithm is controlled by the following parameters:

High threshold: this value sets the digital signal level above which the RF attenuation is

increased (AGCCTRL1 register, allowed values 0...15). The recommended setting for such

parameter is 0x5.

Low thresholds: this allows a better tuning of the low thresholds in case the analog

attenuation steps have a significant spread around the nominal 6 dB attenuation. The

threshold actually used for each step is selected through the bits of the

LOW_THRESHOLD_SEL (AGCCTRL3) register. The recommended setting for Low

Threshold 0 is 0x5, recommended setting for Low Threshold 1 is 0x4. The recommended

value for LOW_THRESHOLD_SEL is 0x10.

Measure time: this parameter sets the measurement interval during which the signal level

is monitored before the AGC attenuation is decreased. In particular, if the signal level is

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