S2-LP datasheet(44/90 Pages) STMICROELECTRONICS

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Block description

S2-LP

44/90

DocID029944 Rev 1

Figure 7: Output power ramping configuration

5.6.2

Transmitter data modes

Direct modes are primarily intended to completely bypass the automatic packet handler, in

order to give the user maximum flexibility in the choice of frame formats. In specific:



Direct through FIFO mode: the packet is written in TX FIFO. The user build the

packet according to his need including preamble, payload and soon on. The data are

transmitted without any processing.



Direct through GPIO mode: the packet bits are continuously read from one of the

GPIO pins, properly configured, and transmitted without any processing. To allow the

synchronization of an external data source, a data clock signal is also provided on one

of the GPIO pins. Data are sampled by the device on the rising edge of such clock

signal; it is the responsibility of the external data source to provide a stable input at

this edge.



PN9 mode: a pseudo-random binary sequence is generated internally. This mode is

provided for test purposes only.

5.6.3

Data FIFO

In the S2-LP there are two data FIFOs, a TX FIFO for data to be transmitted and an RX

FIFO for the received data both of 128 bytes. The SPI interface is used to read from the RX

FIFO and write to the TX FIFO starting from the address 0xFF.

S2-LP 数据表(PDF) 44 Page - STMicroelectronics