S2-LP datasheet(46/90 Pages) STMICROELECTRONICS

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Block description

S2-LP

46/90

DocID029944 Rev 1

The S2-LP is capable of automatically retransmitting the last packet that was stored into

the FIFO (if NMAX_RETX > 0 in the PROTOCOL register and no new packet is loaded into

the TX FIFO between successive re-

transmissions). This feature is useful for “beacon”

transmission or when retransmission is required due to absence of a valid

acknowledgement. Only packets that fit completely in the TX FIFO are valid for the

retransmit feature. When the packet is longer than 128 bytes, the FIFO content after the

transmission is only the last part of the payload. In this case, the FIFO must be reloaded by

the MCU.

The TX FIFO may be flushed by issuing a FLUSHTXFIFO command (see Table 46:

"Commands"). Similarly, a FLUSHRXFIFO command will flush the RX FIFO.

The full / empty status of the TX / RX FIFO is readable on the bits [9:8] of the MC_STATE

registers, and at the same time, the related IRQs will be generated.

In the SLEEP state, the FIFO content is retained only if the SLEEP_B mode is selected (bit

SLEEP_MODE_SEL=1 in the register 0x79).

5.7

Integrated RCO

The S2-LP contains an ultra-low power RC oscillator with accuracy better than 1%. The RC

oscillator frequency is calibrated using as a reference the XO frequency. It depends on two

values: raw (4 bits) and fine (5 bits). The raw value is obtained by a linear search algorithm

in which for each value a counting of half clock reference inside the period of RCO is done.

When the correction is near to the final value, a dichotomy search algorithm.

The RCO calibration starts as soon as the RCO_CALIBRATION bit is set to 1. When it

finishes, the RC_CAL_OK bit is set and the ERROR_LOCK bit is reset.

Moreover, if the RCO_CALIBRATION bit is kept to 1, the device will redo the RCO

calibration as soon a SLEEP command is performed. When the RC CAL OK is set, the

device will switch to the SLEEP state.

It is possible to perform an offline calibration of the RCO using the following procedure:

Enable the RCO CALIB setting the bit to 1

Wait until the RC_CAL_OK becomes 1

Copy the RWT_OUT and RFB_OUT (registers 0x94 and 0x95) out values in the

RWT_IN and RFB_IN fields (registers 0x6E and 0x6F).

Disable the RCO CALIB setting the bit to 0

In this way, the RCO will work with these values. It is advisable to repeat the RCO

calibration to reject effects related to the variation of temperature. It is recommended to use

this procedure if the following SLEEP time (i.e. when using LDC mode) is shorter or

comparable to the calibration time.

By default, the calibration is disabled at reset to avoid using an out-of-range reference

frequency, after the internal clock divider is correctly configured, the user can enable the

RCO calibration by register.

Once calibrated, the RCO generates a clock frequency that depends on the XO frequency

used:

Table 44: RCO Frequency

Ref. Frequency [MHz]

RCO frequency [kHz]

24 or 48

25 or 50

33.33

26 or 52

34.66

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