S2-LP datasheet(18/90 Pages) STMICROELECTRONICS

18 / 90 page

Specifications

S2-LP

18/90

DocID029944 Rev 1

4.6

Frequency synthesizer

Table 14: Frequency synthesizer parameters

Parameter

Test conditions

MHz

Unit

Frequency step size

Out-Loop Divider Ratio = 4

RF carrier phase noise 433 MHz

10 kHz

-111.5

dBc/Hz

100 kHz

-111.8

1 MHz

-124.4

RF carrier phase noise 868 MHz

10 kHz

-104

100 kHz

-104.5

1 MHz

-119.5

RF carrier phase noise 915 MHz

10 kHz

-104

100 kHz

-104

1 MHz

-119

PLL tuning voltage settling time @

(RX/TX transitions: Δf = IF)

Typical intermediate frequency (IF): 300

kHz

µs

PLL calibration time

µs

4.7

Crystal oscillator

Characteristics measured over recommended operating conditions unless otherwise

specified. All typical values are referred to 25 °C temperature, VBAT = 3.0 V.

The device supports crystals in the range [24-26] MHz and [48-52] MHz.

If the crystal is in the [24

–26] MHz range, both the analog and the digital parts must work at

this frequency. Otherwise, if a crystal in the [48-52] MHz range is used, the analog part

must work at this frequency and the digital part at this frequency divided by 2. From now on

in this document the XTAL oscillator will be indicated with

�� and the digital clock with ��.

The divider for the digital part can be set by the PD_CLKDIV bit of the XO_RCO_CONFIG1

in the following way:



if a [48

– 52] MHz crystal is used, this bit must be 0 (digital divider enabled:

�� =

��

)



if a [24

– 26] MHz crystal is used, this bit must be 1 (digital divider disabled:

�� =

��).

The safest procedure to disable the divider without any risk of glitches in the digital clock is

to switch into STANDBY mode, hence, disable the divider through register setting, and then

come back to the READY state.

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