S2-LP datasheet(28/90 Pages) STMICROELECTRONICS

28 / 90 page

Block description

S2-LP

28/90

DocID029944 Rev 1

If the KRM_EN is 1, the SMPS' switching frequency can be set by the KRM word according

to the formula:

Equation 2

�� = ��

��

215

�� is the digital domain frequency (�� if it is 24, 25 or 26 MHz) and (

��

�� is 48, 50

or 52 MHz).

The isolation target is reached by using, for each critical block, a dedicated linear Low-

Dropout Regulator (LDO), which provides typically 1.2 V output voltage, either from battery

level or from SMPS level, depending from the operating mode.

5.2

Power On Reset

The Power On Reset (POR) circuit generates a reset pulse upon power-up which is used to

initialize the entire digital logic. Power-on-reset senses VBAT voltage.

The S2-LP provides an automatic POR circuit, which generates an internal RESETN

(active low) level for a time TRESET. After the VBAT reaches the reset voltage threshold VRRT,

as shown in Figure 5: "Power on reset timing and limits". The same reset pulse is

generated after a step-down on the input pin SDN (VDD>VRRT). This signal will be available

on the GPIO0 pin.

Figure 5: Power on reset timing and limits

At RESET, all the registers are at their default values. A software command SRES allows

to generate an internal RESET of the S2-LP.

Table 33: POR parameters

Parameter

Typ.

Unit

Reset startup threshold voltage

0.5

Reset pulse width

0.7

Power on VDD slope

2.0

V/ms

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