STA321MPL1 datasheet(55/80 Pages) STMICROELECTRONICS

55 / 80 page

DocID029389 Rev 1

55/80

STA321MPL1

Configuration registers (0x77; 0x78; 0x79)

Where x represents the channel and y the biquad number. For example, C0H41 is the b2

coefficient in the fourth biquad for channel 2.

By default, all user-defined filters are pass-through where all coefficients are set to 0, except

the b0/2 coefficient which is set to 0x400000 (representing 0.5). Mix coefficients use only ±1

range.

A special feature inside the digital processing block is available (active when the nshen bit is

set to ‘1’). In the case where poles are positioned at very low frequencies, biquads filters can

generate some audible quantization noise or unwanted DC level. In order to avoid this kind

of effect a quantization noise-shaping capability can be used. The filter structure including

this special feature, relative to each biquad is shown in Figure 9.

The new feature can be enabled independently for each biquad using the I2C registers. The

D7 bit, when set, is responsible for activating this function on the crossover filter while the

other bits address any specific biquads according to the previous table. Channels 1 and 2

share the same settings. Bit D7 is effective also for channel 3 if the related OCFG is used.

Figure 9. Biquad filter structure with quantization error noise shaping

Figure 10. Channel mixer

STA321MPL1 数据表(PDF) 55 Page - STMicroelectronics