STA321MPL1 datasheet(71/80 Pages) STMICROELECTRONICS

71 / 80 page

DocID029389 Rev 1

71/80

STA321MPL1

Configuration registers (0x77; 0x78; 0x79)

PLL input division factor and others (0x74)

By default the STA321MPL1 is able to configure the embedded PLL automatically

depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to

the user, a manual PLL configuration can be used (setting PLLFC to 1). The output PLL

frequency formula is:

Clock manager configuration register (0x75)

PDPDC

PLLFC

PLSTRB

PLSTBB

PLIDF3

PLIDF2

PLIDF1

PLIDF0

000

PLLBYP

PLLDPR

LOWEN

BST32K

Bit

RST

Name

Description

PLLBYP

PLL bypass enable

‘0’: disabled

‘1’: bypassed

PLLDPR

PLL direct programming

‘0’: PLL configuration depends on MCS

‘1’: PLL configuration depends on I2C regs (0x72,

0x73 and 0x74)

1RW

LOWEN

Low clock enable

‘0’: if input clock is too slow, master clock will become

the internal oscillator clock (20 MHz), PLL bypassed

‘1’: disabled

BST32K

Boost oversampling for fs = 32 kHz

‘0’: disabled

‘1’: input oversampling is selected x 3

Fout

Fin

IDF

----------

216

--------

⎝⎠

⎛⎞

when PLLFC = 1

Fout

Fin

IDF

----------

()

when PLLFC = 0

STA321MPL1 数据表(PDF) 71 Page - STMicroelectronics

STA321MPL1 数据表(HTML) 71 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载