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STA321MPL1 数据表(PDF) 29 Page - STMicroelectronics |
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STA321MPL1 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 80 page  DocID029389 Rev 1 29/80 STA321MPL1 Registers 80 5.2.4 Configuration register E (0x04) Each individual channel output can be set to output a binary PWM stream. In this mode, output A of a channel is considered the positive output and output B the negative output. 5.2.5 Configuration register F (0x05) The STA321MPL1 features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through an FFX amplifier. DC signals can cause speaker damage. If HPB = 1, then the filter that the high-pass filter utilizes is made available as a user- programmable biquad #1. Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode, the limiter threshold values are constant and dependent on the limiter settings. D7 D6 D5 D4 D3 D2 D1 D0 C8BO C7BO C6BO C5BO C4BO C3BO C2BO C1BO 00 000 00 0 Bit RW RST Name Description 0RW 0 C1BO Channels 1, 2, 3, 4, 5, 6, 7, and 8 binary output mode enable bits. A setting of 0 indicates ordinary FFX tristate output. A setting of 1 indicates binary output mode. 1RW 0 C2BO 2RW 0 C3BO 3RW 0 C4BO 4RW 0 C5BO 5RW 0 C6BO 6RW 0 C7BO 7RW 0 C8BO D7 D6 D5 D4 D3 D2 D1 D0 PWMS2 PWMS1 PWMS0 BQL PSL DEMP DRC HPB 00 000 00 0 Bit RW RST Name Description 0RW 0 HPB High-pass filter bypass bit: a setting of 1 bypasses internal AC coupling digital high-pass filter Bit RW RST Name Description 1 RW 0 DRC Dynamic range compression/anti-clipping 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode |
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