STA321MPL1 datasheet(33/80 Pages) STMICROELECTRONICS

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STA321MPL1

Registers

Setting the IDE bit enables this function, which looks at the input I²S data and automatically

mutes if the signals are perceived as invalid.

The BCLE bit detects loss of input, MCLK, in binary mode and outputs a 50 % duty cycle.

The LDTE bit actively prevents double triggering of LRCLK.

When active, the ECLE bit issues a device power-down signal (EAPD) on clock loss

detection.

5.2.8

Configuration register I (0x08)

This feature utilizes an ADC on SDI78 that provides power supply ripple information for

correction. Registers PSC1, PSC2, PSC3 are utilized in this mode.

Bit

RST

Name

Description

4RW

IDE

Invalid input detect mute enable:

1: enable the automatic invalid input detect mute

Bit

RST

Name

Description

BCLE

Binary output mode clock loss detection enable

Bit

RST

Name

Description

LDTE

LRCLK double trigger protection enable

Bit

RST

Name

Description

ECLE

Auto EAPD on clock loss

EAPD

PSCE

Bit

RST

Name

Description

PSCE

Power supply ripple correction enable:

0: normal operation

1: PSCorrect operation

Bit

RST

Name

Description

EAPD

External amplifier power-down:

0: external power stage power-down active

1: normal operation

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