| 数据搜索系统,热门电子元器件搜索 |
|
STA321MPL1 数据表(PDF) 17 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STA321MPL1 数据表(HTML) 17 Page - STMicroelectronics |
|
17 / 80 page ![]() DocID029389 Rev 1 17/80 STA321MPL1 I2C bus operation 80 4 I2C bus operation The STA321MPL1 supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data to the bus as a transmitter and any device that reads data as a receiver. The device that controls the data transfer is known as the master and the other is the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA321MPL1 is a slave device in all of its communications. 4.1 Communication protocol 4.1.1 Data transition or change Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition while the clock is high is used to identify a START or STOP condition. 4.1.2 Start condition START is identified by a high-to-low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. 4.1.3 Stop condition STOP is identified by a low-to-high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between the STA321MPL1 and the bus master. 4.1.4 Data input During data input, the STA321MPL1 samples the SDA signal on the rising edge of the clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock. The data can change only when the SCL line is low. 4.2 Device addressing To start communication between the master and the Omega FFX core, the master must initiate with a start condition. Following this, the master sends 8 bits onto the SDA line (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA321MPL1 the I2C interface has two device addresses depending on the SA port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |