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STA321MPL1 数据表(PDF) 26 Page - STMicroelectronics |
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STA321MPL1 数据表(HTML) 26 Page - STMicroelectronics |
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26 / 80 page ![]() Registers STA321MPL1 26/80 DocID029389 Rev 1 5.2.2 Configuration register C (0x02) - serial output formats The STA321MPL1 features a serial audio output interface that consists of 8 channels. The serial audio output always acts as a slave to the serial audio input interface and, therefore, all output clocks are synchronous with the input clocks. The output sampling frequency (fs) is also equivalent to the input sampling frequency. In the case of the PDM input, the serial audio output acts as a master with an output sampling frequency of 8 xfs, 4 xfs or fs depending on the SAOD4 bit. The output serial format can be selected independently from the input format and is done via the SAO and SAOFB bits. D7 D6 D5 D4 D3 D2 D1 D0 SAOD4 SAOFB SAO3 SAO2 SAIO SAO0 000 00 0 Bit RW RST Name Description 0RW 0 SAO0 Serial audio output interface format: determines the interface format of the output serial digital audio interface. 1RW 0 SAO1 2RW 0 SAO2 3RW 0 SAO3 Bit RW RST Name Description 4 RW 0 SAOFB Determines MSB or LSB first for all SAO formats: 0: MSB first 1: LSB first Bit RW RST Name Description 5 RW 0 SAOD4 Enables decimation by 4 on SAO interface for PDM input; no effect for others. 0: div by 1 1: div by 4 (1) 1. To avoid any aliasing on SAO streaming, a low-pass filter needs to be implemented in one of the available user-programmable biquads. |
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