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STA321MPL1 数据表(PDF) 51 Page - STMicroelectronics |
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STA321MPL1 数据表(HTML) 51 Page - STMicroelectronics |
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51 / 80 page  DocID029389 Rev 1 51/80 STA321MPL1 Registers 80 5.2.70 Coefficient write control register (0x4C) Coefficients for EQ and Bass Management are handled internally in the STA321MPL1 via the RAM. Access to this RAM is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this function. One register contains a coefficient base address, five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one register contains bits used to control the write of the coefficient(s) to the RAM. Section 5.3, Section 5.4, Section 5.5, and Section 5.6 give the instructions for reading and writing coefficients. D7 D6 D5 D4 D3 D2 D1 D0 WA W1 00 |
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