STA321MPL1 datasheet(48/80 Pages) STMICROELECTRONICS

48 / 80 page

Registers

STA321MPL1

48/80

DocID029389 Rev 1

5.2.52

Channel 7 and 8 output timing (0x36)

The centering of the individual channel PWM output periods can be adjusted by the output

timing registers. The PWM slot settings can be chosen to ensure that pulse transitions do

not occur at the same time on different channels using the same power device. There are 8

possible settings, the appropriate setting varies based on the application and connections to

the FFX power devices.

5.2.53

Coefficient address register 1 (0x3B)

5.2.54

Coefficient address register 2 (0x3C)

5.2.55

Coefficient b1 data register, bits 23:16 (0x3D)

C8OT2

C8OT1

C8OT0

C7OT2

C7OT1

C7OT0

CnOT[2:0]

PWM slot

000

001

010

011

100

101

110

111

CFA9

CFA8

CFA7

CFA6

CFA5

CFA4

CFA3

CFA2

CFA1

CFA0

000

C1B23

C1B22

C1B21

C1B20

C1B19

C1B18

C1B17

C1B16

000

STA321MPL1 数据表(PDF) 48 Page - STMicroelectronics

STA321MPL1 数据表(HTML) 48 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载