STA321MPL1 datasheet(24/80 Pages) STMICROELECTRONICS

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Registers

STA321MPL1

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DocID029389 Rev 1

5.2

5.2.1

Configuration register A (0x00)

• The internal clock depends on the external clock frequency provided to the XTI pin. The

internal clock can be either 90.3168 MHz or 98.304 MHz. In the case of the XTI, it is

respectively 11.2896MHz or 12.288MHz.

• The relationship between the input clock XTI and the PDM interface clock is determined

by both the MCSn and the IRn (input rate) register bits. IR[1,0] = 11 sets the PDM

interface enable and MCS[2:0] = 011 means XTI = 4*PDM interface clock.

If XTI input is not used, the related pin must be tied to GND.

Interpolation ratio select

Setting the DSPB bit bypasses the biquad function of the FFX core.

COS1

COS0

DSPB

IR1

IR0

MCS2

MCS1

MCS0

011

Bit

RST

Name

Description

0RW

MCS0

Master clock select: selects the ratio between the

input sampling frequency (PDM I/FCLK)and the

input clock (XTI).

1RW

MCS1

2RW

MCS2

Input sampling rate

fs (kHz)

MCS[2:0]

1xx

011

010

001

000

XTI

2*PDM_CK

4*PDM_CK

6*PDM_CK

8*PDM_CK

12*PDM_CK

Bit

RST

Name

Description

DSPB

DSP bypass bit:

0: normal operation

1: bypass of biquad and bass/treble functions

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