STA321MPL1 datasheet(72/80 Pages) STMICROELECTRONICS

72 / 80 page

Configuration registers (0x77; 0x78; 0x79)

STA321MPL1

72/80

DocID029389 Rev 1

Clock manager status register (0x76)

6.5.11

RMS level registers (0x7A, 0x7B, 0x7C, 0x7D)

Two sets of registers are available to monitor the RMS level detected by the zero-mute

block after signal processing.

The measured level for a selected channel is given in 0x7A and 0x7B (zero-mute level) and

0x7C and 0x7D (PWM out level) according to the following expression:

Value(dB) = 20Log(rms[15:0]/(216 x 0.635))

Where rms[15:0] is an unsigned integer formed by:

rms[15:0] = rmsZMH[7:0], rmsZML[7:0] for zero-mute level

rms[15:0] = rmsPOH[7:0], rmsPOL[7:0] for PWM output level

PLLBYS

PLLPDS

OSCOK

LOWCKS

Bit

RST

Name

Description

PLLBYS

PLL bypass status

‘0’: normal

‘1’: bypassed

PLLPDS

PLL power-down status

‘0’: normal

‘1’: standby

OSCOK

Oscillator clock OK

‘0’: not ready

‘1’: ready

LOWCKS

Low clock status

‘0’: normal

‘1’: input clock too slow

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